8085 Microprocessor: Addressing Modes, Interrupts, and Pipeline

Posted on Feb 24, 2025 in Computers

8085 Instruction Addressing Modes

These instructions transfer data between registers, memory, and registers without altering the content. Addressing modes in 8085 are classified into 5 groups:

Immediate Addressing Mode

In this mode, the 8/16-bit data is specified in the instruction itself as one of its operands. For example: MVI K, 20F means 20F is copied into register K.

Register Addressing Mode

In this mode, data is copied from one register to another. For example: MOV K, B means data in register B is copied to register K.

Direct Addressing Mode

In this mode, data is directly copied from the given address to the register. For example: LDB 5000K means the data at address 5000K is copied to register B.

Indirect Addressing Mode

In this mode, data is transferred from one register to another by using the address pointed to by the register. For example: MOV K, B means data is transferred from the memory address pointed to by the register to register K.

Implied Addressing Mode

This mode doesn’t require any operand; the data is specified by the opcode itself. For example: CMP.

Interrupts in 8085

Interrupts are signals that cause the microprocessor to suspend its current operation and execute a specific routine.

1. By Origin:

• Hardware Interrupts: Triggered by external devices (e.g., keyboard, timer).
  Example: INTR, RST 7.5, RST 6.5, RST 5.5 in 8085.
• Software Interrupts: Triggered by program instructions.
  Example: RST n instructions in 8085.

2. By Address:

• Vectored Interrupts: Predefined ISR address.
  Example: TRAP, RST 7.5.
• Non-Vectored Interrupts: ISR address supplied during interrupt acknowledgment.
  Example: INTR.

3. By Masking:

• Maskable Interrupts: Can be disabled/enabled.
  Example: RST 7.5, INTR.
• Non-Maskable Interrupts: Cannot be disabled.
  Example: TRAP.

4. Special:

• TRAP: Non-maskable, highest priority interrupt.
• INTR: Maskable, non-vectored interrupt.

Register vs. Memory

Here’s a comparison between registers and memory:

Four-Segment Instruction Pipeline

A four-segment instruction pipeline divides instruction processing into four distinct stages. Each stage performs a specific task, allowing multiple instructions to be processed simultaneously in different stages, improving overall efficiency.

Four Segments of Instruction Pipeline

1. Fetch (F): The instruction is fetched from memory and loaded into the instruction register.
   Example: Fetch the instruction ADD R1, R2, R3.
2. Decode (D): The fetched instruction is decoded to identify the operation and operands.
   Example: Decode ADD as addition and identify registers R1, R2, and R3.
3. Execute (E): The operation is performed using the ALU or another processing unit.
   Example: Perform R1 = R2 + R3.
4. Write Back (W): The result of the operation is written back to the destination register or memory.
   Example: Store the result in R1.

Pipelining Example

Assume three instructions:

1. ADD R1, R2, R3
2. SUB R4, R5, R6
3. MUL R7, R8, R9

Execution Without Pipelining:

Each instruction is processed sequentially, taking 4 clock cycles each:

ADD: F → D → E → W SUB: F → D → E → W MUL: F → D → E → W Total: 12 cycles.

Execution With Pipelining:

Total: 6 cycles.

Advantages

1. Faster instruction throughput.
2. Efficient use of CPU resources.

Limitations

1. Data and control hazards (e.g., dependency between instructions).
2. Stalls may occur due to memory access delays or branch instructions.

Address Sequencing

• Microinstructions are stored in control memory in groups, with each group specifying a routine.
• To appreciate the address sequencing in a micro-program control unit, let us specify the steps that the control must undergo during the execution of a single computer instruction.
• The transformation from the instruction code bits to an address in control memory where the routine is located is referred to as a mapping process.

The address sequencing capabilities required in a control memory are:

1. Incrementing of the control address register.
2. Unconditional branch or conditional branch, depending on status bit conditions.
3. A mapping process from the bits of the instruction to an address for control memory.
4. A facility for subroutine call and return.

8085 Instruction Addressing Mode with Example

The 8085 microprocessor supports various addressing modes, which define how the microprocessor identifies the operands (data) required for execution of an instruction. Below are the key addressing modes in 8085 along with examples:

1. Immediate Addressing Mode

   In this mode, the operand (data) is specified explicitly within the instruction itself.

   Example: MOV A, #32H
   Here, the value 32H (immediate data) is moved directly into the accumulator A.

2. Register Addressing Mode

   In this mode, the operand is in a register, and the instruction specifies the register.

   Example: MOV B, C
   Here, the content of register C is copied into register B.

3. Direct Addressing Mode

   In this mode, the address of the operand (memory location) is specified in the instruction.

   Example: LDA 2050H
   The data at memory address 2050H is loaded into the accumulator A.

4. Indirect Addressing Mode

   In this mode, the instruction specifies a register pair that holds the memory address of the operand.

   Example: MOV A, M
   Here, the memory address is stored in the HL register pair, and the content of that memory location is moved to the accumulator A.

5. Implicit Addressing Mode

   In this mode, the operand is implied in the instruction, and no specific operand is mentioned.

   Example: CMA
   This complements (inverts) the contents of the accumulator. No operand is explicitly mentioned as it operates only on the accumulator.

Stack and Stack Organization

Stack: A LIFO (Last In, First Out) data structure used for temporary data storage. Managed by the Stack Pointer (SP), which points to the top of the stack.

Stack Operations:

• PUSH: Stores data onto the stack (SP decremented, data stored).
• POP: Retrieves data from the stack (data read, SP incremented).

Usage:

• Subroutine calls (saves return addresses).
• Interrupt handling (preserves processor state).

Example:

• SP = 4000H (initial stack pointer).
• PUSH H: Stores H and L registers to memory 3FFFH and 3FFEH.
• POP B: Retrieves values from 3FFFH and 3FFEH into C and B.

Stack Organization:

• Allocated at higher memory.
• Grows downward (from high to low addresses).

Symbolic Microprogram for Instruction FETCH Routine

The instruction fetch routine retrieves the instruction opcode from memory into the processor for execution.

Steps:

• T1: MAR ← PC

  Load the Program Counter (PC) into the Memory Address Register (MAR).

• T2: Memory Read

  Read the memory at the address in MAR.

• T3: IR ← M[MAR]

  Move the fetched instruction into the Instruction Register (IR).

• T4: PC ← PC + 1

  Increment the Program Counter to point to the next instruction.

Key Components:

• MAR: Holds the memory address to be accessed.
• IR: Stores the fetched instruction.
• PC: Points to the address of the next instruction.

This routine prepares the processor for the decode and execute phases.

Design and Control Logic of Accumulator

Design:

• 8-bit Register:

  Stores data for arithmetic and logical operations.

• Connected to ALU:

  Provides one operand to the ALU and stores results from the ALU.

• Data Path:

  Input/Output lines connected to the data bus.

  Uses latches (flip-flops) for data storage.

• Status Flags:

  Works with flags (e.g., Zero, Sign) to indicate operation results.

Control Logic:

• Control Signals:
• LOAD: Transfers data into the accumulator.
• READ: Sends data from the accumulator to the data bus.
• CLEAR: Resets the accumulator to zero.
• ALU Operations: Performs arithmetic/logical operations.

Micro-Operations:

• Load data from memory/I/O to the accumulator.
• Perform ALU operations using accumulator contents.
• Store results back into the accumulator or memory.

Purpose:

• Acts as a temporary storage for operands and results.
• Facilitates fast data transfer between ALU and memory or I/O devices.

Arithmetic Pipeline

An arithmetic pipeline improves performance by dividing arithmetic operations (e.g., addition, multiplication) into smaller stages that execute simultaneously for multiple inputs.

Key Features:

• Stages: Operations are split into sequential steps (e.g., align, add, normalize).
• Parallelism: Multiple operations overlap across stages.
• Throughput: Processes multiple operations at once, improving efficiency.

Example: Floating-Point Addition

Stages:

1. Align exponents.
2. Add mantissas.
3. Normalize result.
4. Round result.

Execution:

For two operations (A + B and C + D):

Advantages:

• Faster execution (increased throughput).
• Efficient use of hardware.

Limitation: May stall if operations depend on each other.