8085 Microprocessor: Architecture, Instructions, and Applications

Posted on Oct 10, 2024 in Computers

What is the 8085 Microprocessor?

The 8085 microprocessor, developed by Intel in 1976, is an 8-bit microprocessor widely used in embedded systems and small-scale computing devices. It processes data in 8-bit chunks and is a significant part of the 8-bit microprocessor family. Below is a summary of its main functional units:

Functional Units of the 8085 Microprocessor

1. Arithmetic and Logic Unit (ALU)

• Performs arithmetic operations (addition, subtraction) and logical operations (AND, OR, XOR).
• Handles comparisons and increment/decrement operations.

2. Accumulator

• An 8-bit register within the ALU, storing results of arithmetic and logical operations.
• Most operations involve the accumulator and other registers or memory.

3. Registers

• General Purpose Registers: B, C, D, E, H, and L are 8-bit registers used individually or in pairs (BC, DE, HL) to store temporary data.

4. Instruction Register and Decoder

• Instruction Register: Temporarily holds the current instruction fetched from memory.
• Decoder: Interprets the instruction and determines the execution steps.

5. Timing and Control Unit

• Generates control signals to coordinate data flow and manage operations like reading/writing to memory or I/O devices.

6. Interrupt Control

• Handles interrupts (external or internal signals) that pause normal program execution for higher-priority tasks.
• The 8085 has five interrupts: TRAP, RST7.5, RST6.5, RST5.5, and INTR.

7. Serial I/O Control

• Enables serial data transmission and reception through SID (Serial Input Data) and SOD (Serial Output Data) lines.

8. Address and Data Bus

• Address Bus: A 16-bit bus addressing memory locations, allowing access to 64 KB of memory.
• Data Bus: An 8-bit bus transferring data between the processor and memory or I/O devices.

Booth’s Multiplication Algorithm

Booth’s algorithm provides an efficient method for multiplying signed binary integers in 2’s complement representation, minimizing the number of additions/subtractions. It utilizes the fact that strings of 0s in the multiplier require only shifting, and strings of 1s from bit weight 2^k to 2^m can be treated as 2^(k+1) to 2^m. Like other multiplication methods, it involves examining multiplier bits and shifting the partial product. Before shifting, the multiplicand may be added, subtracted, or unchanged based on these rules:

1. Subtract the multiplicand from the partial product when encountering the first least significant 1 in a string of 1s in the multiplier.
2. Add the multiplicand to the partial product when encountering the first 0 (after a previous 1) in a string of 0s in the multiplier.
3. Leave the partial product unchanged if the multiplier bit is the same as the previous one.

Example: Multiplying (-20) and (+13) using Booth’s Algorithm

(Implementation steps would be shown here using a table or diagram for clarity)

Differences between SAP-1 and SAP-2 Architectures

Flynn’s Classification of Computers

M.J. Flynn categorized computer systems based on the number of instruction and data streams processed concurrently. An instruction stream is a sequence of instructions fetched from memory, while a data stream results from operations on data within the processor. Parallel processing can occur in either or both streams.

Flynn’s Classification Categories

1. SISD (Single Instruction, Single Data)

• Represents a single computer with a control unit, memory unit, and processor unit.

2. SIMD (Single Instruction, Multiple Data)

• Represents an organization with multiple processing units under a central control unit.

3. MISD (Multiple Instruction, Single Data)

• Primarily theoretical, as no real systems have been built using this structure.

4. MIMD (Multiple Instruction, Multiple Data)

• Allows all processors in a parallel computer to execute different instructions on different data simultaneously.

Pipelining Concepts

Pipelining is a performance-enhancing technique in computer architecture that allows overlapping execution of multiple instructions. It divides instruction execution into distinct stages, with different parts of multiple instructions processed concurrently, similar to an assembly line.

Key Concepts in Pipelining

1. Stages of Pipelining

A typical pipeline includes stages like instruction fetch (IF), instruction decode (ID), execute (EX), memory access (MEM), and write-back (WB). Each stage performs a specific task, and instructions move through the stages sequentially, maximizing resource utilization.

2. Pipeline Throughput

Pipelining’s primary benefit is increased instruction throughput. By executing multiple instructions concurrently, the processor completes more instructions in a given time, improving performance compared to serial execution.

3. Pipeline Hazards

Pipelining faces challenges called hazards:

• Data Hazards: Occur when instructions depend on results from previous instructions.
• Control Hazards: Arise from branch instructions that disrupt the instruction flow.
• Structural Hazards: Happen when hardware resources are insufficient to support all stages simultaneously.

4. Pipeline Stall

To handle hazards, processors may introduce stalls, temporarily halting instruction progress to resolve dependencies.

5. Pipeline Optimization

Techniques like forwarding, branch prediction, and superscalar execution mitigate hazards and maximize pipelining effectiveness, further boosting performance.

DMA Controller

Direct Memory Access (DMA) utilizes hardware called a DMA controller to access memory. It transfers data between I/O devices and main memory with minimal processor intervention. The DMA controller acts as a control unit, managing data transfer. It includes an address unit that generates addresses and selects I/O devices for data transfer.

DMA Controller Diagram

(A diagram illustrating the DMA controller’s components and connections would be included here)

Instruction Cycle in the 8085 Microprocessor

The 8085 microprocessor’s instruction cycle comprises four fundamental steps:

Steps in the Instruction Cycle

1. Fetch: The microprocessor fetches the instruction from the memory location pointed to by the program counter (PC), which is then incremented.
2. Decode: The fetched instruction is decoded to determine the operation and operands involved.
3. Execute: The microprocessor performs the specified operation on the operands.
4. Store: The execution result is stored in the designated memory location or register.
5. Interrupt Cycle (if needed): If an interrupt occurs, the processor saves its current state and jumps to the interrupt service routine (ISR). After executing the ISR, it resumes from where it left off.

Differences between Hardwired and Microprogrammed Control Units

Address Sequencing and Differences between Isolated and Memory-Mapped I/O

Address Sequencing

In computer architecture, address sequencing is the process of generating a sequence of memory addresses. It’s crucial for efficient data access. Microinstructions, stored in groups within control memory, specify routines for address sequencing.

Differences between Isolated and Memory-Mapped I/O

Evaluating Arithmetic Statements in Two and Three Address Instruction Formats

Two-Address Instructions

Two-address instructions specify two operands or addresses (memory locations or registers). The instruction operates on both operands, and the result may be stored in one of them. The destination address can also hold an operand.

Example: X = (A+B)*(C+D)

MOV R1, A   ; R1 = M[A]
ADD R1, B   ; R1 = R1 + M[B]
MOV R2, C   ; R2 = M[C]
ADD R2, D   ; R2 = R2 + M[D]
MUL R1, R2   ; R1 = R1 * R2
MOV X, R1   ; M[X] = R1

Three-Address Instructions

Three-address instructions specify three operands or addresses. The instruction operates on all three, and the result may be stored in a separate location.

Example: X = (A+B)*(C+D)

ADD R1, A, B ; R1 = M[A] + M[B]
ADD R2, C, D ; R2 = M[C] + M[D]
MUL X, R1, R2 ; M[X] = R1 * R2

Data Manipulation Instructions

Data Manipulation Instructions perform operations on data in registers or memory. They include:

Types of Data Manipulation Instructions

1. Arithmetic Instructions: Perform addition, subtraction, multiplication, and division.
2. Logical Instructions: Perform bitwise AND, OR, XOR, and NOT operations.
3. Shift and Rotate Instructions: Move bits left or right within a byte or word.
4. Increment and Decrement Instructions: Increase or decrease a register’s value by one.
5. Clear and Complement Instructions: Clear or invert a register’s contents.

Instruction Set of the 8085 Microprocessor and Assembly Language Program for 1’s Complement

Instruction Set Categories

1. Data Transfer Instructions: Move data between registers and memory.
2. Arithmetic Instructions: Perform arithmetic operations.
3. Logical Instructions: Perform logical operations.
4. Branching Instructions: Control program flow based on conditions.
5. Control Instructions: Manage processor operations.

Assembly Language Program to Find 1’s Complement

Algorithm

1. Load data from memory location 2013H into the accumulator.
2. Complement the accumulator’s content.
3. Store the accumulator’s content (1’s complement) in memory location 2052H.

Program

Memory Address  Mnemonics  Operands  Comment
2000            LDA        2013H     ; [A] <- [2013H]
2003            CMA                 ; [A] <- [A']
2004            STA        2052H     ; [2052H] <- [A] (1's complement)
2007            HLT                 ; Stop