8085 Microprocessor: Stack Pointer, Program Counter & Interrupts

Posted on Feb 25, 2025 in Hotel Administration and Management

Stack Pointer Functionality

A stack pointer is a small register that stores the address of the last program request in a stack. A stack is a specialized buffer which stores data from the top down. As new requests come in, they “push down” the older ones. The most recently entered request always resides at the top of the stack, and the program always takes requests from the top.

A stack (also called a pushdown stack) operates in a last-in/first-out (LIFO) manner. When a new data item is entered or “pushed” onto the top of a stack, the stack pointer increments to the next physical memory address, and the new item is copied to that address. When a data item is “pulled” or “popped” from the top of a stack, the item is copied from the address of the stack pointer, and the stack pointer decrements to the next available item at the top of the stack.

Program Counter Explained

An exploit kit is a programming tool that allows someone who does not have any experience writing software code to create, customize, and distribute malware.

A program counter is a register in a computer processor that contains the address (location) of the instruction being executed at the current time. As each instruction gets fetched, the program counter increases its stored value by 1. After each instruction is fetched, the program counter points to the next instruction in the sequence. When the computer restarts or is reset, the program counter normally reverts to 0.

In computing, a program is a specific set of ordered operations for a computer to perform. An instruction is an order given to a computer processor by a program. Within a computer, an address is a specific location in memory or storage. A register is one of a small set of data holding places that the processor uses.

Some engineers refer to a program counter as an instruction address register or an address pointer.

Flag Registers in 8085 Microprocessor

The FLAGS register is the status register in Intel microprocessors that contains the current state of the processor.

The flag register in 8085 is an 8-bit register which contains 5 bit positions. These five flags are of 1bit F/F and are known as zero, sign, carry, parity, and auxiliary carry.

Hardware Interrupts

An interrupt is a mechanism by which an I/O or an instruction can suspend the normal execution of the processor and get itself serviced. Generally, a particular task is assigned to that interrupt signal. In the microprocessor-based system, the interrupts are used for data transfer between the peripheral devices and the microprocessor.

There are 6 interrupt pins in the microprocessor used as Hardware Interrupts given below:

TRAP Vector address-0024H
RST7.5 Vector address-003CH
RST6.5 Vector address-0034H
RST5.5 Vector address-002CH
INTR

TRAP Interrupt

It is a non-maskable edge and level triggered interrupt. TRAP has the highest priority and vectors interrupt. Edge and level triggered means that the TRAP must go high and remain high until it is acknowledged. In case of sudden power failure, it executes an ISR and sends the data from main memory to backup memory.

RST 7.5 Interrupt

It has the second highest priority. It is maskable and edge level triggered interrupt. The vector address of this interrupt is 003CH. Edge sensitive means input goes high and no need to maintain high state until it is recognized.

RST6.5 and RST5.5 Interrupts

These are level triggered and maskable interrupts. When RST6.5 pin is at logic 1, INTE flip-flop is set. RST 6.5 has third highest priority and RST 5.5 has fourth highest priority.

INTR Interrupt

It is level triggered and maskable interrupt. The following sequence of events occurs when INTR signal goes high:

The 8085 checks the status of INTR signal during execution of each instruction.
If INTR signal is high, then 8085 completes its current instruction and sends active low interrupt acknowledge signal, if the interrupt is enabled.
On receiving the instruction, the 8085 saves the address of the next instruction on stack and executes received instruction.

Special Purpose Registers in 8085

Accumulator or A register is an 8-bit register used for arithmetic, logic, I/O and load/store operations.
Flag is an 8-bit register containing 5 1-bit flags:
- Sign – set if the most significant bit of the result is set.
- Zero – set if the result is zero.
- Auxiliary carry – set if there was a carry out from bit 3 to bit 4 of the result.
- Parity – set if the parity (the number of set bits in the result) is even.
- Carry – set if there was a carry during addition, or borrow during subtraction/comparison.
Stack pointer is a 16-bit register. This register is always incremented/decremented by 2.
Program counter is a 16-bit register.

Extra – (The 8085 has six general purpose registers to store 8-bit data. These are identified as B, C, D, E, H, L. they can be combined as register pairs BC, DE, and HL, to perform 16 bit operations.)

Software Interrupts

Software interrupt: an interrupt generated within a processor by executing an instruction. Software interrupts are often used to implement system calls because they result in a subroutine call with a CPU ring level change. Spurious interrupt: a hardware interrupt that is unwanted.

The software interrupts of 8085 are RST 0, RST 1, RST 2, RST 3, RST 4, RST 5, RST 6 and RST 7.

A software interrupt is a particular instruction that can be inserted into the desired location in the program. There are eight Software interrupts in 8085 Microprocessor. From RST0 to RST7.

RST0 Vector address -0000H
RST1 Vector address-0008H
RST2 Vector address-0010H
RST3 Vector address-0018H
RST4 Vector address-0020H
RST5 Vector address-0028H
RST6 Vector address-0030H
RST7 Vector address-0038H

(Vector Address = Interrupt Number *8)

Interrupt Service Routine (ISR)

Interrupt means to break the sequence of operation. While the CPU is executing a program an interrupt breaks the normal sequence of execution of instructions & diverts its execution to some other program. This program to which the control is transferred is called the interrupt service routine.

A small program or a routine that when executed services the corresponding interrupting source is called as an ISR. ISR is also called device driver in case of the devices and called exception or signal or trap handler in case of software interrupts.

ALE (Address Latch Enable)

It is the acronym for Address Latch Enable (pin number 30) used to demultiplex the multiplexed lower order address/data bus. During T1 the ALE goes HIGH. When ALE goes HIGH, the latch is enabled.

When the latch is enabled, the output of the latch becomes equal to the output of AD7-AD0, hence demultiplexing of AD7-AD0 to lower order address bus(A7-A0) is achieved.

The higher order address bus is already available as A15-A8.

After first T-state, ALE becomes Low, hence disables the latch. So, the output of latch gets disconnected from the microprocessor.

IO/M (Input/Output / Memory)

It is a status signal. It is used to differentiate between memory locations and I/O operations.

When this signal is low (IO/M = 0) it denotes the memory related operations.
When this signal is high (IO/M = 1) it denotes an I/O operation.

Non-Maskable Interrupt – TRAP

An interrupt that can be disabled by writing some instruction is known as maskable Interrupt otherwise it is called Non-Maskable Interrupt. It is non-maskable edge and level triggered interrupt. TRAP has the highest priority and vectors interrupt. Edge and level triggered means that the TRAP must go high and remain high until it is acknowledged. In case of sudden power failure, it executes an ISR and sends the data from main memory to backup memory. As we know that TRAP cannot be masked but it can be delayed using HOLD signal. This interrupt transfers the microprocessor’s control to location 0024H.

Interrupt Handling Process

We know that the instruction cycle consists of fetch, decode, execute, and read/write functions. After every instruction cycle, the processor will check for interrupts to be processed. If there is no interrupt present in the system, it will go for the next instruction cycle which is given by the instruction register.

If there is an interrupt present, then it will trigger the interrupt handler. The handler will stop the present instruction which is processing and save its configuration in a register and load the program counter of the interrupt from a location which is given by the interrupt vector table. After processing the interrupt by the processor interrupt handler will load the instruction and its configuration from the saved register, process will start its processing where it’s left. This saving the old instruction processing configuration and loading the new interrupt configuration is also called as context switching.

The interrupt handler is also called as Interrupt service routine (ISR). There are different types of interrupt handlers which will handle different interrupts. For example, for the clock in a system will have its interrupt handler, keyboard it will have its interrupt handler for every device it will have its interrupt handler.

The main features of the ISR are:

Interrupts can occur at any time; they are asynchronous. ISRs can call for asynchronous interrupts.
Interrupt service mechanism can call the ISRs from multiple sources.
ISRs can handle both maskable and non-maskable interrupts. An instruction in a program can disable or enable an interrupt handler call.
ISR on beginning of execution it will disable other devices interrupt services. After completion of the ISR execution it will re initialize the interrupt services.
The nested interrupts are allowed in ISR for diversion to other ISR.

Types of Interrupt Handlers

First Level Interrupt Handler (FLIH) is a hard interrupt handler or fast interrupt handler. These interrupt handlers have more jitter while process execution and they are mainly maskable interrupts.
Second Level Interrupt Handler (SLIH) is a soft interrupt handler and slow interrupt handler. These interrupt handlers are having less jitter.

Interrupt Handling Process (Reiterated)