Computer Architecture and Organization Glossary
MAR (Memory Address Register): A CPU register used to hold the address of the memory location being accessed.
1’s Complement Representation: Used in representing binary numbers by complementing each 1 to 0 and each 0 to 1.
2’s Complement Representation: Used in representing binary numbers. Positive values are in sign-magnitude. Negative values are represented by adding 1 to the 1’s complement of the number.
Absolute Address: An address that identifies a memory location without using intermediate references. Usually useful in the design or analysis of sophisticated systems.
Abstraction: Focusing on the big picture, not on the details; ignoring details and concentrating on the big picture of a system. Usually used in analyzing or designing complicated systems.
Access Time: Time needed to position read/write heads of the disk over a specific track and sector. Rotational delay (latency) and seek time should also be considered.
Accumulator: CPU register that holds the results of operations and sometimes the operands.
Active (Intelligent) Backplane: Motherboard design style that moves the CPU or some device and interface controllers to a daughter-board.
ADC (Analog to Digital Converter): Converts analog signals (e.g., voice, music) into digital data to be stored in the memory and to allow editing.
Address Bus: System bus used to transfer addresses in RAM or I/O device.
Address Mapping (Translation): The process of converting a given virtual memory address into a physical memory address to be able to access the memory.
Address Space: Range of addresses (either in RAM or I/O) that can be referenced.
ALU: Part of the CPU that performs arithmetic, logical, and shift operations.
Amdahl’s Law: The law that states that performance enhancement can’t be increased without limits and that it is limited by the amount in which a specific enhancement feature is used.
ASCII (American Standard Code for Information Interchange): A 7-bit standard character set used to represent characters inside the computer. Characters include upper and lowercase letters, digits, special characters, as well as control characters.
ASRAM (Asynchronous RAM): Static RAM that transfers data without using the system clock. It is slower but less expensive than SRAM.
Assembler: A system program that translates a mnemonic assembly language into machine language.
Assembly Language: Low-level, machine-dependent, computer language that has a 1-to-1 correspondence with machine language instructions. It uses mnemonics instead of 1s and 0s.
Asserted Signal: A signal that has the logical value true (or 1).
Associative Memory: Memory whose locations are identified by their contents, rather than their position.
Asynchronous Timing: Timing technique in which the occurrence of events depends on previous events, not on the system clock.
Backplane: A motherboard that mounts add-in cards, called daughter-boards, to add a processor, memory, or other motherboard features.
Base Address: A numeric value used as a reference in address calculation.
Binary Operator: An operator that acts on two operands.
BIOS (Basic Input/Output System): Firmware, resides in ROM, that is responsible for booting the PC, verifying configuration, and providing an interface between hardware and software.
Bit (Binary Digit): A single memory unit (transistor or capacitor) that holds a single binary value (0 or 1).
Boolean Algebra: Mathematics laws used by the processor to perform logical (&, OR, NOT) and data shift operations.
Branch Prediction: A way of solving branch (control) hazards and increasing CPU efficiency by assuming that the branch test will fail and continuing fetching the next instruction.
Bubble (Pipeline Stall): Used to resolve hazards by delaying fetching the next instruction until the required operands are ready.
Buffer: Memory locations used to keep input or output data. It is needed to compensate for the difference in speed between the CPU and the I/O devices.
Bus: Communication path consisting of a collection of lines, on the motherboard, that carries signals, addresses, or data between PC components. A bus can be used by all computer components. Only one component can use a bus at any given time.
Bus Arbitration: The process of determining which bus master will have access permission to the bus next.
Bus Master: The unit that controls and initiates bus communication or request.
Byte: Memory unit that holds 8 bits and can hold one of 256 possible binary values. It is the smallest addressable unit of storage and is normally associated with a single ASCII character.
Cache: A small, fast memory that acts as a buffer to slower, large storage. It is used to enhance CPU performance by reducing access time. It copies and holds instructions and data likely to be needed for the following CPU operations.
Cache Block (Line): Block of data transferred as a unit to or from cache memory.
Cache Coherency: The consistency in the values of data in the different caches of the various processors.
Cache Hit: If the data or address needed by the CPU is already available in the cache.
Cache Memory: Smaller and faster storage used to enhance computer efficiency by increasing access speed to most probably used memory locations. It holds copies of data or instructions likely to be used by the processor. The data is transferred in specified block sizes.
Cache Miss: A situation that occurs when the CPU requests data from the cache and finds out that the data is not available in the cache. In such case, the block containing the desired data or instruction has to be loaded into the cache before processing can continue.
Chipset: A group of standard PC functions combined onto one or more integrated circuits. It provides the software and protocols necessary for the PC components to communicate and control devices plugged into the motherboard.
Clock: Square wave with equal intervals. Used to synchronize CPU operations. Events usually occur at the rising or falling edge of the clock.
Clock Cycle (Clock Period / Tick): Usually refers to the processor clock that runs at a fixed rate and is used to synchronize CPU operations.
Clock Rate: The number of clock cycles that occur in one second. It is the inverse of a clock period and is measured in clock cycles per second.
Clock Skew: The difference in absolute time between the times when two elements see a clock edge.
Clock Speed: Number of cycles per second, measured in MHz (megahertz).
Combinational (Combinatorial) Circuit: Logic circuit whose output is a function of its input only at any given time. There is no storage capability of previous contents of the circuit.
Conditional Branch: Instruction that performs a comparison on values and allows subsequent transfer of control to another part of the program, depending on the result of the comparison.
Control (Branch) Hazard: The situation in which the proper instruction can’t be executed in the correct clock cycle because an incorrect instruction is being fetched.
Control Bus: System bus used to transfer control signals between the processor and other computer components.
Control Unit: Part of the CPU responsible for controlling and coordinating computer operations.
Coprocessor: A secondary processor used for a specific activity (e.g., graphics coprocessor or math coprocessor).
CPI (Clock Cycle Per Instruction): The average number of clock cycles taken by an instruction.
CPU (Central Processing Unit): The heart of the computer that is responsible for executing instructions and controlling all other computer components. It consists of the datapath and control.
Data (Pipeline) Hazard: The situation in which the proper instruction can’t execute in the correct clock cycle because the required data is not available in the cache memory and needs to be fetched from the main memory.
Data Bus: System bus used to transfer data.
Datapath: The part of the CPU that is responsible for the arithmetic and logic operations. It consists of the ALU and register file.
Daughter Board: A circuit board that plugs into a motherboard or backplane board to add additional capabilities to the system.
Decoder: Combinational circuit used to transfer an input signal combination on several input lines into one specific 2n-output lines, depending on the input combination. There is a 1-to-1 correspondence between the input and output.
DIP (Dual Inline Packaging): Common packaging for memory and integrated circuit chips. DIP chips are mounted onto individual sockets directly on the motherboard.
Direct Access: Accessing memory locations directly, independent of their relative position.
Direct-Mapped Cache: The cache type that assigns only one possible location to each cached for each main memory location. A direct-mapped cache could be described as “1-way set associative”, i.e., one location in each set, whereas a fully associative cache is n-way associative (where n is the total number of blocks in the cache). Performance studies have shown that it is generally more effective to increase the number of entries rather than associativity and that 2- to 16-way set associative caches perform almost as well as fully associative caches at little extra cost over direct mapping.
Distributed Memory: Physical memory that is divided into modules, each assigned to a processor in a multi-processor system.
DMA (Direct Memory Access): I/O technique that allows direct data exchange between memory and I/O devices without holding the processor time. The CPU only initializes the I/O request and is interrupted after the transfer is complete. A DMA module controls the rest of the data transfer.
Don’t Care Term: An element of a logical function in which the output doesn’t depend on all the values of the input.
DRAM (Dynamic RAM): RAM implemented using capacitors and that needs to be periodically recharged (refreshed).
DRDRAM (Direct Rambus DRAM): A proprietary DRAM technology that features RAM speeds up to 800 MHz. Developed by Rambus Corporation (www.rambus.com) and Intel.
EB (Exabyte): 1 quintillion bytes.
EEPROM (Electronically Erasable Programmable Read-Only Memory): Commonly used in BIOS chips and can be updated with a process called flashing through specialized software.
Error-Correcting Code: Code used on transmitted signals or characters used to automatically correct errors in transmission.
Error-Detecting Code: Code used on transmitted signals or characters used to automatically detect errors in transmission.
Exclusive-OR Gate (Function): The logic that generates logical value “true” if both input values are different and generates “false” otherwise.
Execute Cycle: The part of the instruction cycle used by the CPU to perform the actions needed by the instruction.
External (Level 2 / Secondary) Cache: Cache usually placed on the motherboard.
Fetch Cycle: The part of the instruction cycle used by the CPU to fetch the instruction to be executed from memory.
Firmware: Micro-code stored in ROM.
Fixed-Point Representation System: Real number representation in which the radix point (decimal point for radix 10) is placed in a fixed location.
Flash Memory: SRAM memory used in portable PCs to extend working storage.
Flip-Flop: A memory unit that holds one binary value and in which the output represents the current state. The next state depends on the current state and the input. A flip-flop’s change of state is usually synchronized by a clock edge.
Floating-Point Representation System: Real number representation in which the number is represented as two distinct parts: mantissa and exponent.
Forwarding (Bypassing): A method used to resolve data hazards by retrieving the data earlier, from the internal buffers, instead of waiting for them to be stored in the registers or memory.
Fully-Associative Cache: Caching technique that allows memory locations to be referenced from any cache line (block). A cache where data from any address can be stored in any cache location. The whole address must be used as the tag. All tags must be compared simultaneously (associatively) with the requested address and if one matches, then its associated data is accessed. This requires an associative memory to hold the tags, which makes this form of cache more expensive. It does, however, solve the problem of contention for cache locations (cache conflict) since a block need only be flushed when the whole cache is full and then the block to flush can be selected in a more efficient way.
Gate: Combinational circuit element that produces an output that resembles a simple Boolean operation (&, OR, or NOT) of the applied input.
GB (Gigabyte): = 1,073,741,824 bytes ≈ 1 billion bytes.
General-Purpose Register: A register that can be used for any purpose.
Global Variable: A variable that can be accessed and used by all parts of a program.
Hexadecimal Numbers: A base-16 number system that represents 16 values (0 to 9 and A to F). Commonly used to represent memory addresses or data.
Hit Ratio: A measure of cache effectiveness = (cache hits / cache misses).
Hz (Hertz): Number of clock cycles per second. Usually given in kHz (kilohertz) or MHz (megahertz).
IC (Integrated Circuit / Chip): A hardware component usually made of silicon that hosts dozens to millions of transistors on a small area.
Immediate (Zero-Level) Address: Contents of an address-part of an instruction that contains the value of the operand directly, rather than its address.
Index Register: Register used to modify operand address or as a counter during program execution. Usually used to control a loop, array usage, or table lookup.
Indexing: Address modification technique using an index register.
Indirect Address: An address of a memory location that contains an address.
Instruction Format: Instruction layout that divides the instruction into fields corresponding to constituents of the instruction (opcode, operands, etc.).
Instruction Set: The complete set of instructions used by a machine.
Internal (Level 1/ Primary) Cache: Cache located on the CPU chip.
Interrupt: An exception that comes from outside the processor. Suspension of execution caused by an event.
Interrupt Handler: A software program segment that is executed when an interrupt occurs.
ISA (Instruction Set Architecture): An abstract interface between the hardware and the lowest-level software of a machine that encompasses necessary information to write a correct machine-language program. It includes the specification of instructions, registers, memory size, etc.
L1 (Level 1) Cache: Cache located closest to the processor. Also called primary cache.
L2 (Level 2) Cache: Cache located outside the processor. Also known as secondary cache.
LAN (Local Area Network): Network connection that carries data in a small geographic area, typically within the same building.
Latency: Wait or delay time, measured in milliseconds. On a hard disk: time needed for the disk to rotate the desired sector under the read/write head. In memory: extra time needed to locate an address in memory.
Link Editor (Linker): A system program that combines independently assembled machine language programs and resolves undefined labels. The resulting code is in executable code form.
Local Variable: A variable that is defined and accessed in a specified module of a program only.
Locality (of Reference) Principle: Tendency of a program to access the same set of memory locations repetitively over a short period of time.
LRU (Least Recently Used) Scheme: A replacement scheme in which the new desired block replaces the block that has been unused the longest time.
M (Mega): 220 = 1,048,576.
Mantissa: In representing floating-point numbers. The part of a floating-point number which, when multiplied by its radix raised to the power of its exponent, gives its value. The mantissa may include the number’s sign or this may be considered to be a separate part.
Memory Buffer Register: A CPU register used to hold data to be stored into or retrieved from a memory location.
Memory-Mapped I/O: Addressing mode for I/O modules and external devices in which a single address space is used for both memory and I/O devices. Same machine instructions can be used.
MESI: Modified/Executable/Shared/Invalid protocol. Used to support cache consistency requirements of multiprocessor systems.
MFLOPS (Mega Flops): A measure of execution speed of a program based on the number of floating-point instructions executed per second. MFLOPS = number of floating-point operations in a program / (execution time x 106).
Microinstruction: Low-level control instruction in which a machine instruction is used to generate control signals.
Micro-operation: Elementary CPU operation, performed during one clock cycle.
Microprocessor: Integrated circuits building the heart of the computer that include ALU, general and special registers, and control units.
Microprogram: Microinstruction sequence.
MIMD (Multiple Instruction Stream, Multiple-Data Stream): The classification under Flynn’s taxonomy of a parallel processor where many functional units perform different operations on different data. Examples would be a network of workstations.
MIPS (Million Instructions Per Second): Measure of execution speed. MIPS = number of instructions in a program / (program execution time x 106).
Miss Penalty: Time needed to fetch a block into cache from a lower level memory, including time to access the block, to transmit the block, and to store it in the cache.
Miss Rate: Fraction of memory accesses not found in cache.
Motherboard: A large printed-circuit board used to host computer components (e.g., microprocessor chip, chipset, RAM, cache, bus structures, I/O ports, etc.).
Multi-Level Cache: Memory hierarchy with multiple cache levels.
Multiplexor: Combinational circuit connecting multiple inputs to a single output. One of the inputs is selected to pass through the output, depending on the selection signal combination.
Multiprocessor: Computer having more than one processor with common main memory and a single address space.
Multiprogramming: Programming mode that allows two or more programs to run interleaved by a single processor.
Nonvolatile Memory: Memory whose contents stay intact even when the power is turned off.
Opcode (Operation Code): Part of an instruction that denotes the operation and format of an instruction.
Operand: Entity on which an operation is performed. Part of an instruction.
Operating System: System software used to control program execution, allocate and manage resources, schedule tasks, control I/O operations, and manage data.
Orthogonality: Independent variable or dimensions. In instruction set context, indicates independency of address mode, number or length of operands with respect to opcode.
Page: A fixed-length memory block that has a virtual address and is exchanged as a unit between two memory types (e.g., RAM and cache or RAM and secondary memory).
Page Fault: A condition that occurs when referencing a memory word that is not in RAM. It causes an interrupt and requires loading the page containing the desired word before the program can continue.
Page Frame: A block in RAM that can hold a page.
Page Table: The table that contains the virtual-to-physical address translation in a virtual memory system. Usually is indexed by virtual page number.
Parity Bit: An extra bit attached to a word and causes the sum of all digits to be either odd or even, depending on the type of parity (odd parity or even parity).
Peer-to-Peer Network: Two or more computers directly connected and directly share the data and hardware resources.
Pipeline: A way of increasing processor performance. Instructions are divided into smaller stages, each stage uses a different resource. More than one instruction can run concurrently, each using a different resource.
PLA (Programmable Logic Array): An array of logic gates interconnected to implement a logic function. It consists of a set of inputs and their corresponding set of complements. It has two stages; the first stage generates the product terms and the second generates the sum terms of the product terms.
Product-of-Sum: A logical expression combines ORed terms (sum) and then applies the AND operator (product) on them.
PROM (Programmable ROM): Semiconductor memory whose contents can be electrically written once by the user.
Pseudo-instruction (Synthetic/Macro Instruction): Variation of assembly language instruction that is expanded by the assembler into a sequence of machine instructions.
Radix (Base): Number representation system.
RAM (Random Access Memory): Memory accessed giving a unique address to each location. Access time is independent of the previous access sequence.
Reference Bit (Use Bit): A field that is set when a page is accessed. It is used to implement the LRU replacement scheme.
Register: High-speed memory element residing in the CPU used to save operands, results, instructions, or addresses. Built out of flip-flops.
Register File: The set of registers inside the CPU that are accessed by supplying the register number and the type of operation needed. In case of writing into the register, the data should be supplied as well.
ROM (Read-Only Memory): Non-erasable semiconductor memory that is written once and can be read as often as needed.
SCSI (Small Computer System Interface): A bus used as a standard for I/O devices.
Seek Time: Time needed for the head actuator to move the read/write head from one track to the next.
Segmentation: Variable-size address mapping scheme in which an address is divided into two parts: a segment number and segment offset.
Sequential Circuit: Logic circuit in which the next state is a function of both the current state and the input. It acts as a memory element.
Set-Associative Cache: A cache that has a fixed number of locations (at least two) where each block can be placed.
This is a compromise between a direct-mapped cache and a fully associative cache where each address is mapped to a certain set of cache locations. The address space is divided into blocks of m bytes (the cache line or block size), discarding the bottom m address bits. An “n-way set associative” cache with s sets has n cache locations in each set. Block b is mapped to set “b mod s” and may be stored in any of the n locations in that set with its upper address bits as a tag. To determine whether block b is in the cache, set “b mod s” is searched associatively for the tag.
Sign-Extend: To increase the size of a data item by replicating the sign bit of the original data item in the high-order bits of the larger, destination data item.
Sign-Magnitude Representation: Number representation used to represent binary integers. The leftmost bit is used to represent the sign (1 for negative, 0 for positive). The remaining bits hold the magnitude of the number.
SIMD (Single-Instruction Stream / Single-Data Stream): Multiprocessor architecture that can perform a single operation on multiple sets of data. One of the processors is used as a master to control other processors.
SIMD (Single-Instruction Stream, Multiple-Data Stream) (or “Data Parallel”): The classification under Flynn’s taxonomy for a parallel processor where many processing elements (functional units) perform the same operations on different data. There is often a central controller that broadcasts the instruction stream to all the processing elements.
SIMM (Single-Inline Memory Module): Memory module consisting of a DRAM chip in special packaging. Soldered on a small circuit board with a 30- or 72- edge connector.
SISD (Single-Inline, Single-Data Stream): Computer classification in Flynn’s taxonomy that refers to the conventional processor.
Snooping Cache Memory: Method for maintaining cache coherency in which all cache controllers monitor (snoop on) the bus to determine whether or not they have the desired block.
Spatial Locality: Locality principle that states that data referencing tends to reference nearby addresses.
SPEC (System Performance Evaluation Cooperative) Benchmark: A set of standard CPU-intensive integer and floating-point benchmarks based on actual programs and used to measure computer performance.
SRAM (Static RAM): RAM implemented with flip-flops. Data holds as long as the power is on. No periodic refreshing is needed.
Stack: A list that is operated on a LIFO (Last-In, First-Out) basis.
Stack Frame (Procedure Call Frame): A block of memory used to hold arguments passed to a procedure, save registers, and allocate space for local variables.
Stack Pointer: A value stored in a register and points to the most recently allocated stack frame.
Sticky Bit: A bit used in rounding in addition to guard and round fractional part of a number.
Structural Hazard: A situation in which an instruction can’t execute in the proper clock cycle because the hardware can’t support the instruction combination at the given time.
Sum-of-Product: A logical expression combines ANDed terms (product) and then applies the OR operator (sum) on them.
Super Pipelining: A technique that increases processor speed by increasing the length of the pipeline. A super-pipelined processor has a pipeline where each of these logical steps may be subdivided into multiple pipeline stages.
Superscalar Pipelining: Technique that replicates the internal computer components to allow multiple instructions to be executed in every pipeline stage.
Superscalar Processor: An advanced pipelining technique in which more than one instruction can execute during one clock cycle, each on a different pipeline stage.
Synchronous Timing: Timing technique in which occurrences of events on a bus are determined by the clock.
System Bus: A bus used to interconnect major computer components (e.g., CPU, memory, and I/O).
Tag: A field in a table containing address information to identify a memory block in which a specific word is found.
TB (Terabytes): = 1,099,511,627,776 bytes ≈ 1 trillion bytes.
TLB (Translation Lookaside Buffer): Used in virtual memory systems. A cache that keeps track of recently used address mapping to avoid an access to the page table. It lists the physical address page number associated with each virtual address page number.
Transistor: Electronic circuit that stores electrical voltage representing one bit. It is the building block of computers.
Truth Table: Table describing logic functions by listing all possible input combinations and their corresponding output values.
Unary Operator: An operator that acts on one operand only (e.g., –5.6, NOT true).
Underflow: A condition that can occur when the result of a floating-point operation would be smaller in magnitude (closer to zero, either positive or negative) than the smallest quantity representable. Underflow is actually (negative) overflow of the exponent of the floating-point quantity. It occurs when a negative exponent is too large to be represented. This means that the number is too small to be represented.
Valid Bit: A field in the table of memory hierarchy indicating data validity in the associated block.
Virtual Address: A memory location accessed by an application program in a system with virtual memory such that intervening hardware &/or software maps the virtual address to real (physical) memory. During the course of execution of an application, the same virtual address may be mapped to many different physical addresses as data and programs are paged out and paged in to other locations.
Virtual Memory: Address space that can be viewed as addressable main memory by the user. They are mapped by the processor into a physical address space. Usually, the virtual address space is larger than the physical address space.
Volatile Memory: Memory that loses its contents when the power is turned off. RAM is an example of volatile memory.
Write Back: A cache architecture in which data is only written to main memory when it is forced out of the cache. Opposite of write-through.
Write Through: A cache architecture in which data is written to main memory at the same time as it is cached. Opposite of write-back.