Computer Architecture: Key Formulas and ISA Comparison
Key Computer Architecture Formulas
Mean Time Between Failures (MTBF) = MTTF + MTTR. Availability (Reliability) = MTTF / MTBF. Failure Rate = 1/ MTTF. Speedup of X relative to Y = Execution timeY / Execution timeX. Speedup = Execution time for entire task without using enhancement / Execution time for entire task using enhancement when possible. Speedup_overall = Executiontime_old / Executiontime_new = 1 / (1 – Fraction_enhanced) + (Fraction_enhanced / Speedup_enhanced). CPU time = CPU clock cycles * clock cycle time = CPU clock cycles / clock rate = IC * Cycles per instruction * clock cycle time = Instructions per program * Clock Cycles per instruction * seconds/clock cycle. CPI = CPU Clock cycles for a program / IC. CPU Clock Cycles = SUM i=1:n ICi * CPIi. CPU Time = CPU Clock Cycles (above) * Clock cycle time.
CPU execution time = IC x CPI x Clock cycle time = IC x (CPIexec + Memory Stall cycles per instruction) x Clock cycle time = (CPU clock cycle + Memory stall cycle) * Clock cycle time = IC * (CPIexec + Memory accesses per instruction x Miss rate x Miss penalty) x Clock cycle time = IC x (CPIexec + Misses per instruction x Miss penalty) x Clock cycle time. CPU clock Cycles = IC * CPI; Memory stall cycles = Number of Misses * Miss Penalty = IC * Misses per instruction * Miss penalty = IC * Memory accesses per Instruction * Miss Rate * Miss penalty = IC * Memory reads per Instruction * Read miss Rate * Read miss penalty + IC * Memory Writes per Instruction * Write miss Rate * Write miss penalty. AMAT = Hit time + Miss rate * Miss Penalty. Misses per instruction = Memory accesses per instruction x Miss rate
Instruction Set Architecture (ISA) Comparison
ISA:
Stack Architecture
Pros: Good code density (implicit operand addressing top of stack); Low hardware requirements; Easy to write a simpler compiler for stack architectures.
Cons: Little ability for parallelism or pipelining; Data is not always at the top of stack when needed, so additional instructions like TOP and SWAP are needed; Difficult to write an optimizing compiler for stack architectures.
Accumulator Architecture
Pros: Very low hardware requirements; Easy to design and understand.
Cons: Accumulator becomes the bottleneck; Little ability for parallelism or pipelining; High memory traffic.
Memory-Memory Architecture
Pros: Requires fewer instructions (especially if 3 operands); Easy to write compilers for (especially if 3 operands).
Cons: Very high memory traffic (especially if 3 operands); Variable number of clocks per instruction (especially if 2 operands) CPI is different.
Memory-Register Architecture
Pros: Some data can be accessed without loading first (stored in registers); Instruction format easy to encode (using addressing modes); Good code density.
Cons: Variable number of clocks per instruction; May limit number of registers since some of these are used to save some operands.
Load-Store Architecture
Pros: Simple, fixed length instruction encoding; Instructions take similar number of cycles; Relatively easy to pipeline.
Cons: Higher instruction count; Not all instructions need three operands; Dependent on good compiler.
{Most common- Memory Register. Fastest- Register-Register. Which register is specified by small “address” (3 to 6 bits for 8 to 64 registers); Load and store have one long & one short address: One and half addresses; Arithmetic instruction has 3 “half” addresses.