Computer Interconnection: Buses, Channels, and Interfaces

Posted on Dec 15, 2024 in Computers

Selective Cache Invalidation

To invalidate content selectively, the cache is flushed before a read operation. This forces an update of the main memory content. For a write operation, the processor I/O or channel acts as an extension of DMA, further reducing CPU interference. Traditionally used in mainframes, it’s now common in file servers. These specialized processors execute I/O programs, typically located in the main memory.

Types of Channels

  1. Selector: Controls multiple fast devices, transferring data to/from one device at a time.
  2. Multiplexer: Handles I/O for several slow devices simultaneously. A byte multiplexer manages character transfers, while a block multiplexer handles data blocks for faster devices.

Interconnection Bus

Introduction

Functional units in a computer need to communicate via interconnection lines. These lines support transfers between the processor, memory, and I/O. A bus is a shared communication channel connecting multiple subsystems. Each line transmits a single bit of information.

Advantage: Versatility and low cost. Disadvantage: It’s a bottleneck, limiting system performance. The challenge is to meet communication demands while connecting many I/O devices.

Desirable features: Heterogeneity, scalability, low latency, and high bandwidth. The main design problem is speed, limited by physical factors and the need to support diverse devices.

The industry is transitioning from shared parallel loops to point-to-point high-speed switches due to increasing transmission speeds.

Bus Structure

Bus lines are classified into three groups:

  1. Data Lines (D): Transmit data between modules. The number of data lines determines the maximum bits transmitted simultaneously.
  2. Address Lines: Designate the source or destination of data. The width of the address bus determines the maximum addressable memory and I/O devices.
  3. Control Lines: Manage access and use of data and address lines, signaling requests, acknowledgments, and the type of information being transmitted.

Electrical Characteristics

Buses can be unidirectional (with one transmitter and multiple receivers, or multiple transmitters and one receiver) or bidirectional.

Typical control lines include: memory write, memory read, I/O write, I/O read, transfer acknowledge, bus request, bus grant, interrupt request, failure detection, clock, and reset.

Basic Bus Usage

To send data:

  1. Obtain bus access.
  2. Transfer data via the bus.

To request data:

  1. Obtain bus access.
  2. Transfer the request using control and address lines.
  3. Wait for the data.

Bus Hierarchies

Common bus types include processor-memory buses, I/O buses, and backplane buses (e.g., PCI). The benefits of a single bus decrease with the number of connected devices. Solutions involve multiple buses, often organized hierarchically.

Bus Design

Key design considerations include:

  • Bus Type: Dedicated or multiplexed.
  • Bus Width: Address and data lines.
  • Timing: Synchronous or asynchronous.
  • Number of Bus Masters: One or multiple.
  • Arbitration Method: Centralized or distributed.
  • Data Transfer Type: Read, write, read-modify-write, read-after-write, block, and transaction start.

Timing

Synchronous Bus

Includes a clock signal. Communication is fixed and ruled by the clock signal. It assumes shipments arrive correctly.

Advantages: High speed and simple implementation.

Disadvantages: Not suitable for devices with large speed differences; requires careful design due to clock bias. Memory buses are usually synchronous.

Asynchronous Bus

No clock signal. Data transmissions are coordinated by a handshaking protocol.

Advantages: Allows connection of devices with different speeds, scales well with the number of devices and technological changes, and allows longer distances.

Disadvantages: Slower due to synchronization overhead, requires additional control lines, and is difficult to predict transition times. I/O buses are usually asynchronous.

Arbitration Scheme

Manages multiple bus masters based on priority and fairness.

Arbitration Techniques

  1. Serial: Bus access is granted based on device priority.
  2. Parallel Centralized: Multiple lines are used for requests, and a centralized arbiter selects the bus master.
  3. Distributed by Self-Selection: Each device independently determines if it has the highest priority.
  4. Distributed by Collision Detection: Devices request the bus independently; collisions are detected, and a pattern determines the bus master.

Data Transfer Types

  • Write (Multiplexed): Address cycle followed by data cycle.
  • Read (Multiplexed): Address cycle, wait, then data.
  • Read-Modify-Write: Address, wait, read data, then write data.
  • Read-After-Write: Address, write data, wait, then read data.
  • Block Data Transfer: Address followed by multiple data transfers.
  • Write (Non-Multiplexed): Data and address sent simultaneously on different lines.
  • Read (Non-Multiplexed): Similar to write but takes longer.

Design Decisions

Design choices include:

  • Bus Width: Independent or multiplexed data and address lines.
  • Bus Width: Wider buses are faster, narrower buses are cheaper.
  • Transfer Size: Single word or block transfers.
  • Bus Masters: Single or multiple masters (requiring arbitration).
  • Transaction Start: With or without transaction start (affects bandwidth and latency).
  • Timing: Synchronous or asynchronous.

Standard Bus Examples

ISA Bus

Now obsolete, developed by IBM for its PC XT and AT. It became a de facto standard. Specifications: 8-bit, 4.77 MHz (XT) / 16-bit, 8 MHz (AT). IBM later developed the MCA bus (32-bit, 10 MHz), but it failed due to lack of backward compatibility. EISA was a successful alternative (32-bit, 33 MB/s) with ISA support.

The system bus bottleneck became apparent in demanding graphics applications. Solutions included:

  1. VESA Local Bus: Direct access to memory at processor speed, but strongly dependent on the processor.
  2. PCI: Developed by Intel, isolates the CPU while maintaining memory access.

PCI Bus

A 64-bit bus (often implemented as 32-bit) with 33 or 66 MHz clocks. It’s processor-independent, simple, economical, and expandable. It allows interconnection of other buses (like ISA) and provides improvements such as shared interrupt request lines (IRQ) and bus mastering for DMA modules. PCI-X, AGP, and PCI Express followed.

PCI-X

Designed to increase performance (up to 1 GB/s) for high-bandwidth devices like Gigabit Ethernet and fiber optics. It is compatible with PCI.

External Interfaces

Interfaces for communication between I/O modules and peripherals. They can be parallel or serial, point-to-point or multipoint. Point-to-point links are typical for keyboards and parallel ports, while multipoint links are used for external buses, SCSI, USB, and FireWire.

SCSI Interface

Designed for connecting numerous peripherals to personal computers and servers. Initially a parallel interface with 8 lines and 5 MB/s data rate. Later versions increased the number of lines and devices. It uses a bus structure but is often a chain of devices. New external interface standards include:

Traditional serial ports are used for slower peripherals, while parallel ports are used for faster devices. New fast serial interfaces offer advantages in speed and cost. They feature simple connections, automatic device detection, hot-swapping, and robust connectivity.

USB

A root hub connects to the main bus, allowing a star topology with up to 127 devices. Cable length is up to 5 meters per segment. (1.5 Mb/s, 12 Mb/s, 480 Mb/s for USB 2.0).

FireWire

Transfer rates up to 400 MB/s (initially) and 800 MB/s. Up to 63 devices on a single bus. It offers higher throughput than USB for storage and video devices. It allows peer-to-peer communication without a host. Up to 100 meters per segment.

AGP

An interface designed by Intel in 1996 for graphics cards, providing a dedicated 32-bit, 66 MHz channel for the graphics processor to access main memory. It is not a shared medium. It is based on the PCI 2.1 specification and is designed specifically for graphics hardware. Initial versions allowed a single slot, but later revisions removed this limitation.

PCI Express

Designed to replace PCI and AGP, based on point-to-point serial channels, allowing full-duplex communication. It provides a fast interface for I/O devices. It uses a network of serial channels, dynamically switched, allowing multiple simultaneous communications. Channels can be grouped to increase bandwidth. A single channel provides almost double the bandwidth of PCI, 4 channels are equivalent to PCI-X and AGP, and 8 channels are faster. It does not replace the memory bus or support communication between processors.