Computer Memory: Types, Functions, and Addressing

Posted on Dec 21, 2024 in Computers

Chapter 4: Computer Memory Fundamentals

  1. 8196 bytes are equal to 8KB.
  2. Memory access is the activity of a component (mostly the processor) to locate a memory location and perform a read or write operation.
  3. The two main memory operations are reading and writing.
  4. The difference between SRAM and DRAM lies in their ability to retain a bit of value. SRAM retains the value while energized, while DRAM requires frequent recharging of energy to keep the bit value.
  5. Total memory content is defined by the number of address bits.
  6. With 13 bits, a 32K x 8 memory configuration has 256K bits (32 * 8 * 1024 = 256 * 1024).
  7. A 16K x 16 memory configuration with 14 bits has 256K bits (16 * 16 * 1024 = 256 * 1024).
  8. A 14-bit configuration with 8 bits per location results in 128K bits, which is equivalent to a 16K x 8 memory configuration (16 * 8 * 1024 = 128 * 1024).

Memory Registers and Buses

  1. REM (Memory Address Register): Temporarily stores the address to access a memory location and indicates whether it’s a read or write operation.
    RDM (Memory Data Register): Temporarily stores information being transferred between the CPU and main memory during read or write operations.
  2. Address Bus: Connects the CPU to main memory, transferring address bits. It’s unidirectional; information always travels from the CPU to main memory.
    Data Bus: Connects the CPU to main memory, transferring data bits. It’s bidirectional; bits travel from the CPU to main memory during write operations and vice-versa during read operations.
    Control Bus: Connects the CPU to main memory, transmitting control signals like read and write commands.

Read and Write Operations

  1. Read Operation:
    1. The address (e.g., 100) is sent on the address bus.
    2. The CPU sends a read signal on the control bus.
    3. Main memory activates the corresponding cell.
    4. Main memory sends the data through the data bus.

    Example:

    CPU (100) –> Address Bus –> Main Memory

    CPU <– Control Bus <– Read Signal <– Main Memory

    CPU <– Data Bus <– Data (007) <– Main Memory

  2. Write Operation:
    1. The address (e.g., 100) is placed on the address bus.
    2. The data (e.g., 007) is placed on the data bus.
    3. The CPU sends a write signal on the control bus.
    4. Main memory writes the data to the specified address.

    Example:

    CPU (100) –> Address Bus –> Main Memory

    CPU (007) –> Data Bus –> Main Memory

    CPU –> Control Bus –> Write Signal –> Main Memory

    Main Memory (Address 100) now contains 007.

Memory Calculations and Concepts

  1. a) 20 bits b) Two cells c) 8M bits
  2. a) 32,768 in decimal b) 15 bits c) RDM = 8 bits, REM = 15 bits d) 256 bits
  3. a) REM = 16 bits, RDM = 12 bits b) 768K bits
  4. 2C7A16 (Hexadecimal)
  5. Approximately 40,000 bits

Main Memory vs. Cache Memory

  1. FeatureMain MemoryCache Memory
    Access Time60-100 nanoseconds5-10 nanoseconds
    CapacityHigh (typically 256MB – 512MB or more)Medium (typically 256KB – 4MB, internal and external)
    Data TemporarinessAverage (data remains for a duration smaller than the program’s execution)Little (data remains for a very short time)

ROM, PROM, and EPROM

  1. No. I/O memory allows read and write operations directly by application programs, while ROM only allows read operations.
  2. PROM is not reusable (it can only be written once), while EPROM can be erased (using special processes) and rewritten.
  3. The difference is in the data recording process. In the original ROM (mask), data is recorded during manufacturing. In PROM, recording is done individually after its manufacture.
  4. Shadowing is the possibility of creating a copy of ROM in RAM (faster).
  5. 10.8 nanoseconds

Additional Memory Concepts

  1. Due to their high speed, most registers require the ability to use such devices for improved processing performance.
  2. For the entire program to be stored in main memory from startup until the system is turned off, a part of the main memory needs to be non-volatile.
  3. Memory address position vs. its content (data).
  4. ECC (Error Correcting Code) is a group of bits calculated by an algorithm that handles data bits to be transmitted, generating protection bits. Upon reception, the system performs the same calculation and attempts to correct data bits if errors are detected.
  5. Decoded
  6. 3 of 8
  7. 37 bits
  8. 15 bits
  9. 3584 positions
  10. The number of bits (digits) of numbers that represent each address, defined by the processor manufacturer.
  11. a) 1.03 MB b) 10.25 MB c) 124 images
  12. 32,768 bytes or 32KB
  13. Not necessarily. More processing power usually means greater width of registers, arithmetic units, data buses, clock frequency, pipeline stages, etc. While most programs are stored in memory.
  14. This statement is valid when combined with the specification of a block transfer between disk and main memory. Since the disk transfer time is slow (milliseconds), it’s beneficial to transfer more data at once and have greater main memory capacity to avoid frequent disk access.

Chapter 5: Cache Memory

  1. Main memory: 19 address bits. Cache address field: Tag: 5 bits, Set: 7 bits, Byte: 7 bits.
  2. The assembly addressing step, since each block of main memory is directly associated with a set, is similar to the direct mapping method.

  3. a) Address format:

    | Tag (8 bits) | Line (5 bits) | Byte (3 bits) |

    Total: 16 bits

    b) Address of line 3 is 00011.

    c) Cache capacity is 256 bytes (2(5+3) = 28 = 256).

  4. Its organization may differ depending on the user’s perspective:

    a) Physically: Organized in a continuous sequence of N cells, generally one byte wide.

    b) Cache Control System: Organized in groups of bytes called lines (or blocks), formed by contiguous cells in main memory.

    c) Operating System: Main memory is seen as a bunch of bytes (contiguous cells) called pages.

  5. The size of a line is always greater than the size of a cell to exploit the principle of spatial locality. However, if it’s too large, it can extrapolate the advantage of spatial locality by bringing in bytes that are not used in sequence, thus losing time and space.
  6. Due to the principle of locality.
  7. In direct mapping, each block is permanently associated with a cache line. In the associative method, this is not the case, and a decision must be made on which line to remove to make way for the block being sought.

  8. Address format:

    | Byte (4 bits) | Set (7 bits) | Tag (8 bits) |

    Total: 19 bits

  9. a) 28 bits b) Address line: 11, 110, 101, 001, 111
  10. Both are cache organization levels. Read cache (internal) schema. Unified cache: There is only one component (L1) containing data and instructions. In the divided cache system, there are two separate devices: one L1 cache for data and another L1 cache for instructions.

  11. Address format:

    | Tag (9 bits) | Set (5 bits) | Byte (12 bits) |

    Total: 26 bits

  12. Because it is composed of electronic elements (transistors) that require electricity for their operation (SRAM).

  13. a) Address format:

    | Tag (11 bits) | Line (13 bits) | Byte (4 bits) |

    Total: 28 bits

    b) Address examples:

    • 1011111000101 0011010000 1100 (Tag: 1011111000101, Line: 0011010000, Byte: 1100)
    • 0001101000110 00101111000 1111 (Tag: 0001101000110, Line: 00101111000, Byte: 1111)

    c) 288,768 bits

    d) Block address: 0010111010010

  14. a) 2,293,760 bits b) 2,523,136 bits c) 2,154,496 bits
  15. a) 16 MB b) 4K lines c) 16 bits d) 256 blocks / 16 lines a) 1 MB b) 1K lines c) 256 sets d) 16 bits