Digital Logic Circuits: Half Subtractor, Decoder, Flip-Flops, and Shift Registers

Posted on May 14, 2024 in Design and Engineering

Half Subtractor

A half subtractor is a digital logic circuit that performs the subtraction of two binary bits. It has two inputs, A and B, and two outputs, Difference (d) and Borrow (b). The output d is the difference between the two inputs, A and B, and output b represents a borrow, indicating that the subtraction of B from A requires borrowing from the next digit in a larger binary number.

A half subtractor can be used in combination with other half subtractors to build a full subtractor circuit, which can perform binary subtraction of larger binary numbers.

Decoder

A decoder is a combinational circuit that converts a binary input into a specific output line. It essentially “decodes” the input to select one of multiple output lines based on the binary value of the input.

To implement an 8 x 1 multiplexer (MUX) using 4 x 1 MUXes, you can cascade two levels of MUXes. Here’s how you can do it:

  1. Use a 3-to-8 decoder to generate the select lines for the first set of 4 x 1 MUXes.
  2. Connect the inputs of the 4 x 1 MUXes to your data inputs.
  3. Use the output of the decoder as the select lines for the first set of 4 x 1 MUXes.
  4. Take the outputs of the first set of 4 x 1 MUXes as inputs to the second set of 4 x 1 MUXes.
  5. Use the remaining select input to the second set of 4 x 1 MUXes to choose the final output

This way, you can effectively implement an 8 x 1 MUX using two levels of 4 x 1 MUXes and a 3-to-8 decoder.

Clocked RS Flip-Flop

A clocked RS flip-flop is a type of flip-flop that uses a clock signal to control when it reads and updates its inputs. Here’s an explanation along with a logic diagram and characteristic table:

Logic Diagram:

[Image of clocked RS flip-flop logic diagram]

Characteristics Table:

| S | R | Q(t) | Q(t+1) | |—|—|—|—| | 0 | 0 | X | Q(t) | | 0 | 1 | 0 | 0 | | 1 | 0 | 0 | 1 | | 1 | 1 | X | Undefined |

.X represents “don’t care” or any value.

.Q(t) represents the current state of the output.

.Q(t+1) represents the next state of the output.

.The flip-flop reads the inputs S (Set) and R (Reset) only when the clock signal (CLK) is high (1).

.When S=0 and R=0, the flip-flop holds its current state.

.When S=0 and R=1, the flip-flop resets to 0 regardless of the current state.

.When S=1 and R=0, the flip-flop sets to 1 regardless of the current state.

.When S=1 and R=1, it’s in an undefined state, so it’s not used.

This setup ensures stable transitions and avoids metastability issues.

Realize JK Flip-Flop from SR Flip-Flop

To realize a JK flip-flop from an SR flip-flop, you can use the following logic:

  1. Connect the S and R inputs of the SR flip-flop to the J and K inputs of the JK flip-flop, respectively.
  2. Add an AND gate with inputs J and Q’ (the complement of the output of the JK flip-flop), and connect its output to the S input of the SR flip-flop.
  3. Add another AND gate with inputs K and Q, and connect its output to the R input of the SR flip-flop.

This configuration ensures that when J=1 and K=0, the flip-flop toggles to its complement state, and when J=0 and K=1, the flip-flop resets to 0. When both J and K are 0, the flip-flop maintains its current state.

Parallel-In Parallel-Out Shift Register

A Parallel-In Parallel-Out (PIPO) shift register is a type of digital circuit that can store multiple bits of data simultaneously and shift them in and out in parallel.

Here’s how it works:

.”Parallel-In” means that multiple bits of data can be loaded into the register simultaneously through parallel input lines.

.”Parallel-Out” means that multiple bits of data can be read

out from the register simultaneously through parallel output lines.

So, if you have, say, an 8-bit PIPO shift register:

.You can load 8 bits of data into it at once using the parallel input lines.

.You can read those 8 bits out simultaneously using the parallel output lines.

.Additionally, you can shift the contents of the register left or right, effectively moving the bits within the register.

Binary Parallel Adder

A binary parallel adder is a digital circuit that adds two binary numbers in parallel form and produces the arithmetic sum of those numbers in parallel form. It consists of full adders connected in a chain , with the output carry from each full-adder connected to the input carry of the next full-adder in the chain.

Reflected Binary Code (RBC)

The reflected binary code (R

BC), also known as reflected binary (RB) or Gray code after Frank Gray, is an ordering of the binary numeral system such that two successive values differ in only one bit (binary digit).

Johnson counter also known as creeping counter, is an example of synchronous counter. In Johnson counter, the complemented output of last flip flop is connected to input of first flip flop and to implement n-bit Johnson counter we require n flip-flop.It is one of the most important type of shift register counter. I