Digital Logic Design: Counters, Flip-Flops, and FSMs

Posted on Oct 30, 2024 in Computers

Designing a Mod-10 Asynchronous Counter

Designing a mod-10 asynchronous counter using T flip-flops involves creating a counter that counts from 0 to 9 (binary 0000 to 1001) and then resets to 0.

Counter States

The counter will have four T flip-flops (T0, T1, T2, T3) since 2⁴ = 16, which covers the 10 states needed.

State Transitions

The counter will transition as follows:

T Flip-Flop Input Requirements

For T flip-flops, the input T must be set to toggle the output on each clock pulse based on the current state.

T Input Derivation

1. T0 toggles on every clock pulse: T0 = 1
2. T1 toggles when Q0 changes from 1 to 0: T1 = Q0
3. T2 toggles when Q1 and Q0 are both 1: T2 = Q1 AND Q0
4. T3 toggles when Q2 and Q1 are both 1: T3 = Q2 AND Q1

T Inputs Summary

Master-Slave JK Flip-Flop

Overview

The Master-Slave JK Flip-Flop is used for memory storage and synchronization. It consists of two JK flip-flops: the Master and the Slave. The Master is triggered on the clock’s rising edge, while the Slave is triggered on the falling edge.

Structure

1. Master Flip-Flop: Captures the input state during the clock’s high phase.
2. Slave Flip-Flop: Captures the output state during the clock’s low phase.
3. Inputs: J, K, and Clock (CLK).
4. Outputs: Q and Q’ (complement of Q).

Working Mechanism

1. Clock Pulse: The Master captures inputs when the clock is high, and the Slave outputs the state when the clock is low.
2. Input States:
   • J = 0, K = 0: No change; Q remains the same.
   • J = 0, K = 1: Reset state; Q becomes 0.
   • J = 1, K = 0: Set state; Q becomes 1.
   • J = 1, K = 1: Toggle state; Q changes to the opposite state.

Reduced State Table and State Diagram

To create a reduced state table and state diagram, follow these steps:

1. Identify States: List all states and transitions.
2. Create Initial State Table: Show current state, input, next state, and output.
3. Minimize State Table: Identify and eliminate equivalent states.
4. Create Reduced State Table: Update the table with reduced states.
5. Draw Reduced State Diagram: Represent reduced states and transitions visually.

Designing a 4-Bit Synchronous Mod-6 Counter

Step 1: Understand Mod-6 Counter

Counts from 0 to 5 (0000 to 0101) and resets to 0.

4-Bit Right Shift Register

A 4-bit right shift register shifts bits to the right using four D flip-flops.

Finite State Machines (FSM)

A Finite State Machine (FSM) is a computational model with finite states, transitions, and actions.

Types

1. Deterministic FSM (DFSM): One transition per state and input.
2. Non-Deterministic FSM (NFSM): Multiple possible transitions.

Applications

• Digital Circuit Design
• Control Systems
• Protocol Design
• Software Engineering
• Compiler Design
• Pattern Recognition
• Automata Theory
• Embedded Systems