Embedded System Communication Protocols and Memory Concepts

Posted on Mar 29, 2025 in Computers

UART Communication Protocol Details

UART (Universal Asynchronous Receiver/Transmitter) mode operates as follows:

  1. Idle State: A non-return-to-zero (NRZ) state where the serial line maintains a logic state of 1.
  2. Start Bit: A signaling flag indicating the beginning of a byte, marked by a 1-to-0 transition. The receiver detects this transition at the middle of the bit interval (T).
  3. Data Bits: Following the start bit, typically 8 data bits are transmitted on the TxD line and received on the RxD line over a period of 8*T. The receiver detects each bit at the middle of its interval (T). Earlier circuits allowed setting the number of data bits to 5, 6, or 7 instead of 8.
  4. Control/Error Detection Bit: An optional parity bit (P-bit) used for detecting parity errors. Depending on the processing circuit at the receiver, this bit can also interpret the preceding byte as an address, command, or parity information instead of data.
  5. Stop Bit: A flag bit indicating the end of the byte, requiring at least one stop bit at Logic 1. Earlier circuits allowed setting the number of stop bits to 1.5 or 2 instead of 1.
  6. Disconnected State: A Zero (Z) state, where a disconnected serial line shows a logic state of 0.

HDLC Protocol Details

HDLC (High-level Data Link Control) is a standard protocol for the data link layer, enabling synchronous communication between two devices on a network. It exists in two formats: Standard HDLC and Extended HDLC.

The sequence of bits in an HDLC frame is:

  1. Flag Bits: Frame start signaling bits, represented as 01111110.
  2. Address Bits: 8 bits for the destination address in Standard HDLC format, and 16 bits in the extended format.
  3. Control Field: Distinguishes between the three frame types used in HDLC: information, control, and unnumbered frames.
  4. Information Field: Contains the data payload. HDLC does not specify its length, but implementations usually define a maximum length.
  5. Frame Check Sequence (FCS): Contains error-checking bits, typically 16 bits, with an option to increase to 32 bits.

Serial Bus Communication Protocols

I2C (Inter-Integrated Circuit) Bus

The I²C (Inter-Integrated Circuit) bus is a popular synchronous serial bus for interconnecting multiple device circuits, such as flash memory, touch screens, temperature sensors, and pressure sensors within a system (e.g., a plant). It simplifies connections and provides a common protocol.

Specific I/O devices can connect using interfaces like an I²C controller. The I²C bus uses only two lines:

  • SCL (Serial Clock): Carries the clock signal.
  • SDA (Serial Data): Carries bi-directional data.

Device Addressing: Each device on the bus has a unique 7-bit address for data transfers. A Master device initiates communication and can address up to 127 other Slave devices. The Master typically includes a processing element (like a microcontroller) with an I²C bus interface circuit.

Slaves and Masters: Each Slave device can optionally have its own I²C controller and processing element. Multiple Masters can be connected to the same bus.

CAN (Controller Area Network) Bus

CAN is a Distributed Control Area Network, commonly used in applications like automotive embedded systems. A CAN bus line usually connects to a CAN controller, which interfaces between the line and the host node.

The CAN controller typically includes:

  • A Bus Interface Unit (BIU) with buffers and drivers.
  • A protocol controller.
  • Status and control registers.
  • Receiver buffers and message objects.

These units connect to the host node via a host interface circuit, managing communication between the physical and data link layers.

USB (Universal Serial Bus)

USB facilitates serial transmission and reception between a host and peripheral devices. It supports four types of data transfer:

  • Controlled data transfer
  • Bulk data transfer
  • Interrupt-driven data transfer
  • Isochronous transfer

USB Protocol Features:

  • Connects up to 127 devices to a single host.
  • Standards include:
    • USB 1.1: Low speed (1.5 Mbps, 3m channel) and Full speed (12 Mbps, 5m typical, 25m max with hubs).
    • USB 2.0: High speed (480 Mbps, 5m typical, 25m max with hubs).
    • Wireless USB: High speed (480 Mbps, 3m range).

Parallel Bus Device Protocols

PCI (Peripheral Component Interconnect) Bus

The PCI bus is a parallel bus enabling a host computer to communicate simultaneously (32-bit or 64-bit) with devices like network interface cards (NICs) or graphics cards. It allows networked I/O devices in distributed embedded subsystems to communicate over a common parallel bus. PCI connects subsystems with various I/O devices at high speeds over very short distances (<25 cm) without needing specific interfaces for each device.

PCI-X Bus Enhancements

PCI-X offers higher bandwidth than standard PCI, ranging from 133 MBps up to 1 GBps. Key features include:

  • Backward compatibility with existing PCI cards.
  • Suitable for high-bandwidth devices (e.g., Fibre Channel, Gigabit Ethernet, clustered processors).
  • Maximum throughput up to 1066 MBps (for PCI-X 2.0).
  • Supports 8, 16, 32, or 64-bit transfers.
  • 6U cards may contain additional pins for user-defined I/Os (relevant to CompactPCI).
  • Supports live insertion (Hot-Swap).
  • Can support two independent buses on the backplane (CompactPCI feature).
  • Supports Ethernet, InfiniBand, and StarFabric (Switched fabric systems).
  • Note: Some features listed relate closely to CompactPCI (cPCI), a form factor using PCI/PCI-X signaling.

Read-Only Memory (ROM) Fundamentals

ROM stands for Read-Only Memory. It is non-volatile memory from which data can only be read, not easily written to after manufacturing. Embedded systems use ROM for storing firmware (the ROM image) and flash memory for saving non-volatile data.

Various types of ROM include:

MROM (Masked ROM)

The earliest ROMs were hard-wired devices containing pre-programmed data or instructions. MROM programming occurs during IC fabrication. It is inexpensive for large-scale manufacturing.

PROM (Programmable ROM)

PROM (One-Time Programmable ROM – OTP ROM) is read-only memory that a user can modify only once using a PROM programmer. Once written, a PROM is not erasable. Uses: Storing unique identifiers like smart card numbers or personal information.

EEPROM (Electrically Erasable Programmable ROM)

EEPROM can be programmed and erased electrically, typically thousands of times. Unlike EPROM (which requires UV light for erasure), EEPROM allows selective erasing and programming of individual bytes or locations. This makes reprogramming flexible but slower. Uses: Storing configuration data, current date/time, or port status.

Flash Memory

Flash memory is a type of EEPROM where blocks or sectors of bytes can be erased very quickly (in a ‘flash’). Uses: Storing firmware, digital camera pictures, SMS/MMS messages, and general non-volatile data storage.

Understanding Memory Maps

A memory map is essentially a table or database detailing the structure of memory within a computer system. It shows the allocation of address ranges to different memory types (ROM, RAM, EEPROM, Flash) and I/O devices. The map reflects the available addresses for memory blocks and provides a description of the memory and I/O components in the system hardware.

DMA (Direct Memory Access) Operation

Direct Memory Access (DMA) is a feature allowing I/O devices to read from or write to memory directly, without involving the CPU for every byte transfer. A dedicated DMA controller manages these transfers.

DMA Process:

  1. The DMA controller requests control of the system bus from the CPU using a bus request signal.
  2. The CPU completes its current bus cycle and grants control to the DMA controller via a bus grant signal.
  3. Before the transfer, the CPU programs the DMA controller with the starting memory address, the number of words/bytes to transfer, and the transfer direction (read/write). Key registers in a typical DMA controller include:
    • Starting Address Register: Specifies the beginning memory location for the transfer.
    • Length Register: Specifies the amount of data to transfer.
    • Status Register: Allows the CPU to monitor and control the DMA operation.
  4. Once granted bus mastership, the DMA controller performs the read/write operations directly between the I/O device and memory, using the standard bus signals.
  5. After completing the transfer, the DMA controller releases the bus by deasserting the bus request signal, prompting the CPU to deassert the bus grant and regain control.

Interrupt Handling in Systems

In system programming, an interrupt is a signal sent to the processor by hardware or software, indicating an event that requires immediate attention. It alerts the processor to a high-priority condition, causing it to suspend its current execution.

The processor responds by:

  • Suspending its current activities.
  • Saving its current state (context).
  • Executing a specific function called an Interrupt Service Routine (ISR) or interrupt handler to deal with the event.

This interruption is temporary. After the ISR finishes, the processor restores its saved state and resumes its normal activities.

Interrupt Sources and Types

There are two main types of interrupts:

  1. Hardware Interrupts: Triggered by hardware devices, either internal or external to the processor. Internal sources (e.g., timers, DMA controllers) and external sources (e.g., I/O pins) vary depending on the specific processor or microcontroller family.
  2. Software Interrupts: Generated by software instructions (e.g., INT n in x86, SWI m in ARM). These are often used to request operating system services or handle software-detected errors or exceptional conditions during execution.

ISR (Interrupt Service Routine) Mechanism

An ISR is a dedicated piece of code (a small program or function) that the processor executes when a specific interrupt occurs. Every interrupt source typically has a corresponding ISR.

When an interrupt occurs, the typical mechanism is:

  1. The processor finishes the current instruction (usually).
  2. Further interrupts (often of the same or lower priority) may be masked (disabled).
  3. The processor saves the current context (e.g., program counter, status register) onto the stack.
  4. The processor determines the source of the interrupt and jumps to the corresponding ISR’s starting address (often via an interrupt vector table).
  5. The ISR executes to handle the event.
  6. Upon completion, the ISR executes a special return instruction (e.g., IRET, RTE).
  7. The processor restores the saved context from the stack.
  8. Interrupts are re-enabled (if they were masked).
  9. The processor resumes execution of the interrupted program.