Intel 8255 Parallel Port Interface: Modes & Features

Posted on Mar 6, 2025 in Computers

Intel 8255 Parallel Port Interface Device

The Intel 8255 is a general-purpose, programmable I/O device with 40 terminals. It features 24 I/O pins that can be individually programmed in two groups of 12 and has three modes of operation. It contains three programmable 8-bit parallel ports (A, B, and C). Each port has a corresponding register, and there is a control register for the port.

Formatting the Control Word

The control word is used to program the two groups of interface ports on the 8255. The first three bits program the mode and form of group B. The following four bits (D3 to D6) program the mode and form of Group A (consisting of port A and the lower half of Port C).

Mode 0 – Basic Input/Output

  • Assigns I/O to each of the three ports.
  • Does not use a handshaking protocol for data exchange.
  • Data are simply read from or written to the ports.
  • Output is latched.

Basic Features of Mode 0

  • Two 8-bit ports and two 4-bit ports.
  • Any port can be input or output.
  • Outputs are latched.
  • Inputs are not latched.

Mode 1 – Strobed Input/Output

Data transfer for I/O is performed using handshaking signals. Ports A and B use lines from Port C to generate or accept these handshaking signals in strobe mode.

Basic Features of Mode 1

  • Each group contains an 8-bit data port and a 4-bit control port.
  • Each port can be used for input or output.
  • Both inputs and outputs are latched.
  • The 4-bit control port is used for handshaking.

Functions of I/O Modules

  • Timing and control
  • Communication with the processor
  • Communication with peripheral devices
  • Temporary data storage
  • Error detection

Three techniques:

Programmed Input/Output

Input/Output operations.

Scheduled I/O: Data is exchanged with the module. The processor executes a program that directly controls the I/O operation, including testing the device status, sending read/write commands, and transferring data.

Interrupt-Driven I/O: With this technique, the processor issues an I/O command, continues to execute other instructions, and is interrupted by the I/O module when it has completed its work.

Direct Memory Access (DMA)

Data is transferred from the peripheral to memory without processor intervention, using a specific DMA device.

8086 Interrupt Handling

Upon detecting an interrupt, the 8086 sends an Interrupt Acknowledge. The interrupting device responds by sending an 8-bit data value on the bus, called an interrupt number. Each device uses a different number to identify its own service routine. The process of sending control signals back and forth is called Hand-Shaking. It is necessary to identify the interrupting device. We say that a type-n interruption occurs when a device uses an interrupt number N to interrupt the 8086. The transfer to an interrupt routine is similar to a procedure call; before the transfer, the 8086 saves the registers on the stack.

Interrupt Sequence

  1. The device sends an interrupt signal to the microprocessor.
  2. The processor completes the current instruction.
  3. The processor checks for interrupts. If one is present, it sends an acknowledgment signal to the device that originated it. This signal causes the device to clear the interrupt.
  4. The microprocessor pushes the Program Status Word (PSW) and the instruction address (PC) onto the control stack.
  5. The processor loads the new address related to the interrupt.
  6. The rest of the processor status information (registers) is saved.
  7. The interrupt is processed.
  8. The processor state information is restored.
  9. The PSW and PC are restored.

Interrupt Identification Techniques

  • Multiple interrupt lines
  • Software polling
  • Daisy Chain (Hardware Polling with Vector)
  • Bus Arbitration