Microcontroller Architecture and Communication Protocols

Posted on Jan 14, 2025 in Computer Engineering

Microcontroller Architecture

MCU Components: CPU, RAM, Flash, Bus, Peripherals, Pin Mux, Interrupts, Clocks.

Peripheral Examples

Timers, GPIO, UART, I2C, SPI, ADC, DAC, DMA.

I/O Types and Mechanisms

  1. Programmed I/O:
    • CPU polls the device continuously in a loop, checking for readiness.
    • Wastes CPU cycles, useful for simple, non-time-critical applications.
  2. Interrupt-driven I/O:
    • Device sends an interrupt signal to the CPU when it’s ready.
    • CPU can perform other tasks while waiting.
  3. Direct Memory Access (DMA):
    • DMA controller takes over data transfer between peripherals and memory.
    • Offloads data transfer tasks from the CPU.

Interrupt Handling

Interrupt Process:

  1. CPU issues a command, peripherals operate independently.
  2. Peripheral interrupts CPU when ready.
  3. CPU saves context and executes the interrupt handler (ISR).
  4. After servicing, CPU restores context and resumes its task.

Multiple Interrupts: Priority-based handling ensures higher-priority interrupts preempt lower-priority ones.

Direct Memory Access (DMA)

DMA Process:

  1. CPU instructs DMA: provides instructions like read/write command, device address, memory location.
  2. DMA manages data transfer, CPU continues other tasks.
  3. DMA sends interrupt to CPU on completion.

DMA Cycle Stealing: DMA momentarily halts CPU access to transfer data.

DMA Configurations:

  1. Single Bus (Detached DMA), uses the bus twice.
  2. Integrated DMA, uses the bus once per transfer.
  3. Separate I/O Bus: DMA has its own bus, reducing CPU suspension.

Interrupt Example – STM32F4

Cortex-M4 Nested Vectored Interrupt Controller (NVIC):

  • Manages up to 240 interrupts with programmable priority.
  • Interrupt Latency is ~12 cycles.

NVIC Registers:

  • NVIC_ISERx: Set Enable Registers.
  • NVIC_ICERx: Clear Enable Registers.
  • NVIC_IPRx: Interrupt Priority Registers.

DMA and NVIC in STM32F4

  • Enable Interrupts: NVIC_EnableIRQ(IRQn).
  • Disable Interrupts: NVIC_DisableIRQ(IRQn).
  • Set Priority: NVIC_SetPriority(IRQn, priority).

Cortex-M4 Processor Details

  • Operating Modes: Thread Mode for normal processing, Handler Mode for interrupt processing.
  • Privilege Levels: User (limited) vs Privileged (OS tasks).

Exception Return

  • Return to Thread Mode: Processor loads EXC_RETURN to PC.
  • Pop Context: Restores registers from the stack.

Supervisor Call (SVC)

Allows user-mode programs to request privileged operations from the OS.

Feedback Systems

Key Points:

  • Feedback is used in almost all automatic control systems.
  • Feedback can be either negative or positive.
  • If the gain of the forward path is A, the gain of the feedback path is B and the feedback is subtracted from the input then:

If AB is positive and much greater than 1, then G  1/B

  • Negative feedback can be used to overcome problems of variability within active amplifiers.
  • Negative feedback can be used to increase bandwidth, and to improve other circuit characteristics.

G = A/1+AB

Communication Protocols

Asynchronous

No clock is shared between protocols.

Synchronous

Master has a clock.

Serial

Data is sent one or a few bits at a time.

Parallel

A word is sent at a time.

Inter System Protocol

Used between two systems/devices.

Intra System Protocol

Used internally.

Mode of Communication

  • Simple -> one direction
  • Half Duplex -> one direction at a time
  • Duplex -> both sides can transmit at the same time

UART – Universal Asynchronous Receiver/Transmitter

It is a very old protocol, but many people use it for intercommunication 921600

SPI Introduction

Synchronous Full Duplex Master / Slave SPI Interface

SCLK MOSI MISO nSS

Synchronous Half Duplex Multi Master / Slave

I2C Introduction

Two Line Interface Software Addressable Multi Master with CD Serial, 8 bit Oriented, Bidirectional with 4 Modes On Chip Filtering

I2C Bus Features

Example Signals A Complete Data Transfer Bus Speeds

  • Bidirectional Bus
    • Standard Mode – 100 Kbit/s
    • Fast Mode – 400 Kbits/s
    • Fast Mode Plus – 1 Mbits/s
    • High Speed Mode – 3.4 Mbits/s
  • Unidirectional Bus
    • Ultra Fast Mode – 5 Mbits/s

Uses Push-Pull Drivers (No Pullups)

CAN Introduction

Asynchronous Half Duplex Multi Master / Slave

Example Versions

  • Absence of node addressing – Message identifier specifies contents and priority
  • Lowest message identifier has highest priority
  • Non-destructive arbitration system by CSMA with collision detection
  • Simple Transmission Medium – Twisted pair – CAN H and CAN L

USB Architecture – Hubs

Allows many USB devices to share a single USB port.

USB devices with some incorporated intelligence.

Increase the logical and physical fan out.

Single upstream connection and one-many down stream connection.

Smart wire passing data between the peripheral and Host.

Direct connection exists between host and peripherals.

Two kinds of Hubs:

  • Bus Powered Hub: Draws power from the host computer’s USB interface.
  • Self Powered Hub: Has a built-in power supply.

USB Architecture – Peripherals

Receive and respond to the commands from the host. E.g. Mice, Keyboard, Joysticks.

Two types of Peripherals:

  • Standalone
  • Compound Device

USB Power Management

  • Peripherals connected regardless of the power state.
  • A pair of wires to supply power to the peripherals.
  • Manage power by enabling and disabling power to devices.
  • Removes electrically ill-behaved systems from the network.

USB Endpoints

End point is a unique point in the device which is the source or the receiver of the data.

End point has a definite address associated with it.

Codes indicate the type of transfer.

16 end points within each device each end point has a 4-bit address.

End point “0” reserved for control transfers.

Negative Feedback – A Summary

All negative feedback systems share some properties:

  1. They tend to maintain their output independent of variations in the forward path or in the environment.
  2. They require a forward path gain that is greater than that which would be necessary to achieve the required output in the absence of feedback.
  3. The overall behavior of the system is determined by the nature of the feedback path.

Unfortunately, negative feedback does have implications for the stability of circuits.