Microcontroller Timers and Pin Configuration
Time Counters
Mode 0: The counter register is configured as 13-bit. When the maximum value transition occurs (THx.7 THx.6 … THx.1 THx.0 TLx.4 TLx.3 … TLx.0) = 1111111111111 to zero, the Interrupt flag is activated (TF0, for x = 0 or TF1, for x = 1). It is similar to Mode 1; however, in this case, the 16 bits of the counter register are used (pair TH/TL, THx.0 TLx.7 with THx.7 … … TLx.0); that is, the Interrupt flag is activated when the transition from FFFFh to 0000h occurs in TH/TL. In a counting cycle, up to 65,536 events can be detected (counting from 0 to 65535).
Mode 2: The counter register is set to an eight-bit register. The existence of an overflow in TL (eight bits) causes an Interrupt flag activation, which automatically reloads with the content of the HT register. That is, only 256 events are possible; however, the execution of specific counting restart instructions is unnecessary.
Mode 3: When Timer/Counter 0 is not scheduled to work, the pair set to TH0/TL0 is a set of two independent registers. The TF0 and TF1 flags are controlled by the counter registers of timer 0, respectively, TL0 and TH0. Timer 1 is available for some operations to control the data transmission rate through the serial port. The control of the Interrupt flags process is as follows: Timer 0 operates as a non-automatic reload; that is, when there is a TL0 overflow, the TF0 flag is activated. The TF1 flag is activated when there is an overflow in TH0 (eight-bit count), and this is increased at a rate of 1/12 of the oscillator frequency when TR1 = 1; that is, the events that increase from TH0 are the signal transitions of TR1.relog. The function ‘relog’ is a signal (pulse train) equal to fosc/12 frequency.
In any of the two modes of operation allowed for event counting, the TH and TL registers can be controlled internally or externally. In internal control mode, the software starts the count when the conditions impose TRx = “1” and Gate = “0”. In external control mode, the count is unlocked through the imposition of the state Gate = “1”, software, low level, and not pin \INTx, Hardware. Both internal and external control modes can be used independently. The events detected are counted on a pin (T0 or T1) transitions or above the signal appointed by relog.
Pin Configuration
VSS – Ground connection. VCC – Power supply. XTAL1 and XTAL2 – Input and output of the internal oscillator. RST – Reset input, active state is low. ALE – Address Latch Enable – Output that drives the generated addresses, used to validate the least significant eight bits of the addresses in external memory operations. It can also be used to excite peripheral clock inputs. PSEN – Program Store Enable – Output used to access external program memory. This memory is accessed when low-level impulses occur on that line. EA – External Access Enable – Input to select the program memory block (internal or external) with low addresses – 0000H to 1111H. In processor versions that have internal program memory, this entry must be connected to Vcc when you want to use that memory, and to ground when you plan to use external memory.
P0.7 to P0.0 – Port 0, bidirectional data input and output. This port is not available when using external program memory, as its pins are used to transfer data (D7 to D0 of the data bus) and addresses (A7 to A0 of the address bus). In external memory access operations, program or data, the addresses and data are multiplexed in the time domain, with the demultiplexing done externally by the ALE controlled devices. P1.7 to P1.0 – Port 1, bidirectional. It is the only port whose pins are dedicated to data input and output. P2.7 to P2.0 – Port 2, bidirectional, used in external memory operations, supports the most significant eight bits of the address (A15 to A8). P3.7 to P3.0 – Port 3, bidirectional. Alternatively, all the pins of this port can be used for specific purposes. The special functions reserved for each pin are as follows:
- RxD (P3.0) – Data input in serial transmission mode.
- TxD (P3.1) – Data output in serial transmission mode.
- INT0 (P3.2) – External interrupt 0 input.
- INT1 (P3.3) – External interrupt 1 input.
- T0 (P3.4) – Timer 0 excitation input.
- T1 (P3.5) – Timer 1 excitation input.
- WR (P3.6) – Output control of write operations in external memory.
- RD (P3.7) – Output control of read operations in external memory.
All ports are bidirectional and can be used as inputs or outputs. The operations can change the process bitwise or byte by byte. However, it should be noted that the use of any line of a port as input implies that the last value written to the respective internal latch has been “1”. All ports, except P0 (which has an open-drain configuration), have outputs tied to Vcc internal pull-ups and can excite up to four LS-TTL type inputs (eight, if not Port 0).