MIPS Architecture and Datapath: Key Concepts
EC 1:
The MIPS add, addi, and sub instructions may result in an exception. True
A decoder is a logic block that has an n-bit input and 2n outputs where all outputs are asserted for each input combination. False
A multiplexor is also called a selector, where its output is one of the inputs that is selected by a control. True
A datapath element that has storage is called a State element. A register is a State element. An ALU is a Combinational element.
Asserted: The signal is logically high or true. True
An edge-triggered clock methodology means that any values stored in a sequential logic element are updated only on a clock edge, which is a quick transition from low to high or vice versa. True
We can use the word asserted to indicate a signal that is logically high and assert to specify that a signal should be driven logically high. True
A rising clock edge refers to the clock changing from 0 to 1.
The design of register file can read from 2 registers and write to 1 register during the same clock cycle. True
The design of register file allows writes to a register during the same cycle that the same register is read. False
The inputs carrying the register number to the register file are all 5 bits wide, whereas the lines carrying data values are 32 bits wide.
A register write must be explicitly indicated by asserting the write control signal. True
A register read must be explicitly indicated by asserting the read control signal. False
For an R-type instruction with 3 register operands, we need to read 2 data from the register file.
For an R-type instruction with 3 register operands, we need to write 1 data word into the register file.
For an R-type instruction with 3 register operands, to write a data word, we will need 2 inputs for the register file.
For an R-type instruction with 3 register operands, we will need a total of 4 inputs for the register file.
For an R-type instruction with 3 register operands, we will need a total of 2 outputs for the register file.
For the load instruction lw $t1, offset_value($t2), the value read from memory must be written into the register file in the specified register, which is $t1.
For the store instruction sw $t1, offset_value($t2), the value to be stored must also be read from the register file where it resides in $t1.
For the data memory, the control signals should be MemWrite = 0 & MemRead = 1 for a load instruction.
For the data memory, the control signals should be MemWrite = 1 & MemRead = 0 for a store instruction.
The sign extension unit has a 16-bit input that is sign-extended into a 32-bit result appearing on the output. True
For the beq instruction, branch taken refers to the situation where the branch target address becomes the new PC when the condition is true. True
In the MIPS architecture for a branch instruction, the branch target address is given by the sum of the offset field of the instruction and the address of the instruction following the branch.
If the Zero signal out of the ALU unit shown in the right implementation is asserted, we call Branch taken.
EC 2:
For the beq instruction, branch taken refers to the situation where the branch target address becomes the new PC when the condition is true. True
In the MIPS architecture for a branch instruction, the branch target address is given by the sum of the offset field of the instruction and the address of the instruction following the branch.
Which of the following is correct for a load instruction referring to the right datapath? MemtoReg should be set to cause the read data from the data memory to be sent to the register file.
Which of the following is correct for an R-type instruction referring to the above datapath? PCSrc should be set to cause the sequential following instruction with address PC+4 to be written into the PC.
Which of the following is correct for a store instruction referring to the above datapath? ALUSrc should be set to cause the sign-extended 16-bit offset field from the instruction to be sent to the ALU as the 2nd input.
Which of the following is correct for an R-type instruction referring to the above datapath? ALUSrc should be set to cause the Readdata2 from the RF to be sent to the ALU as the 2nd input.
The single-cycle datapath conceptually must have separate instruction and data memories due to the fact that the processor operates in 1 cycle and cannot use a single-ported memory for 2 different accessed within that cycle.
The MIPS ALU defines 5 different arithmetic and logic operations depending on 4 ALU control inputs. For the branch equal operation, the 4 ALUctl lines should be 0110.
The MIPS ALU defines 5 different arithmetic and logic operations depending on 4 ALU control inputs. For the store word instructions, the 4 ALUctl lines should be 0010.
The MIPS ALU defines 5 different arithmetic and logic operations depending on 4 ALU control inputs. For the load word instructions, the 4 ALUctl lines should be 0010.
The MIPS ALU defines 5 different arithmetic and logic operations depending on 4 ALU control inputs. For the slt word instructions, the 4 ALUctl lines should be 0111.
The MIPS ALU defines 5 different arithmetic and logic operations depending on 4 ALU control inputs. For the logic AND instructions, the 4 ALUctl lines should be 0000.
The MIPS ALU defines 5 different arithmetic and logic operations depending on 4 ALU control inputs. For the logic AND instructions, the 2-bit ALUOp control lines should be 10.
The MIPS ALU defines 5 different arithmetic and logic operations depending on 4 ALU control inputs. For the lw instructions, the 2-bit ALUOp control lines should be 00.
The MIPS ALU defines 5 different arithmetic and logic operations depending on 4 ALU control inputs. For the beq instructions, the 2-bit ALUOp control lines should be 01.
The MIPS ALU defines 5 different arithmetic and logic operations depending on 4 ALU control inputs. For the subtraction instructions, the 2-bit ALUOp control lines should be 10.
The MIPS ALU defines 5 different arithmetic and logic operations depending on 4 ALU control inputs. The 4-bit ALU control input uses a small control unit that has inputs coming from the 6-bit function fields of the instruction.
- b. 2-bit control called
ALUOp - c. Both a & b
The ALU output for the branch-on-equal instruction is used to determine the PC+4 added with the sign-extended, lower 16 bits of the offset shifted left by 2 in the instruction field, as the new branch target address if the result of the subtraction in the ALU is not zero. False
For LW and SW instructions, the ALU function is the same.
If the instruction is OR, then as well as examining the ALUOp bits, the ALU control will also examine Instruction[5:0]
The main control unit sends 2 bits to the ALU control.
The control unit enables a write to the register file using the RegWrite signal.
When MemToReg is 0, the data appearing at the register file’s data input comes from the ALU result.
When MemToReg is 1, the data appearing at the register file’s data input comes from the Read data from DM.
The control unit’s Branch output will be 1 for a branch equal instruction. However, the branch’s target address is only loaded into the PC if the ALU’s Zero output is 1. Otherwise, PC is loaded with PC + 4.
Assume the current instruction is beq $t1, $t2, offset, and $t1 is 90 while $t2 is 85. How will the PC be updated next? PC+4
The ALU is used for both branch on equal and jump instructions. False
What type of instruction will the upper right datapath perform? (Only highlighted functional units are used) Arithmetic instruction
What type of instruction will the upper right datapath perform? (Only highlighted functional units are used) Jump
Slide examples:
Zybooks:
A datapath element whose output values depend only on the present input values is called a combinational element.
A datapath element that has internal storage is called a state element.
Element E has two inputs a and b, and one output z. The following fully defines z: [a|0011], [b|0101], [z|0101]. Element E is a combinational element.
Element F has input b and output z, originally 0. If b changes from 0 to 1, z changes to 1 and stays 1 even after b returns to 0. If b later changes from 0 to 1 again, z changes back to 0. And so on. Element F is a state element.
An ALU is a combinational element. A register is a state element. A clock input is present on a state element. A sequential element is another name for a state element.
If the instruction is SW, then ALUOp should be 00. If the instruction is SW, then the ALU’s four control inputs should be 0010.
ALU performs a subtraction operation: ALUOp = 01
The second input to the ALU comes from the B register. ALUSrcB = 00
The first ALU operand is the PC. ALUSrcA = 0
Memory contents at the location specified by the Address input is replaced by the Write data input. MemWrite = 1
The contents of ALUOut (the branch target address) are sent to the PC for writing. PCSource = 01
Instruction fetch: To fetch an instruction from memory what is the value of MemRead? 1
Instruction decode/register fetch: To compute the branch target address which may be used in the next step, what is the value of ALUOp? 00
Arithmetic-logic (R-Type) instruction: To perform the operation specified by the function code, what is the value of ALUOp? 10
Jump instruction: to write the jump address to PC, what is the value of PCWrite? 1
Memory reference: for a store, MemWrite should be set to what value? 1
Memory read completion: this instruction has an extra step to load data that has been written to MDR in the previous steps to be copied to the register file. MemtoReg should be set to what value to make the copy from MDR to register happen? 1
How many states are in the FSMs for controlling the following types of instructions? Memory reference instructions: 4. Branch instructions: 1. Jump instructions: 1. R-type completion: 2.
Since the jump instruction does not depend on the register values or on computing the branch target address, it can be completed during the second state, rather than waiting until the third. False
The control signal PCWriteCond can be replaced by PCSource[0]. False
In processor X’s pipeline, an add instruction in stage 3 should use the ALU. A branch instruction in stage 4 also should use the ALU. Both instructions cannot simultaneously use the ALU. Such a situation is a structural hazard. True
MIPS implementations tend to have numerous structural hazards. False
Does the following cause a data hazard for the 5-stage MIPS pipeline?
i1: add $s0, $s1, $s2
i2: add $s3, $s0, $s4
Yes
Does the following cause a data hazard for the 5-stage MIPS pipeline?
i1: add $s0, $s1, $s2
i2: add $s3, $s1, $s4
No
Does the following cause a data hazard for the 5-stage MIPS pipeline?
i1: add $s3, $s3, $s4
No
The following causes a data hazard for the 5-stage MIPS pipeline
i1: add $s0, $t0, $t1
i2: sub $t2, $s0, $t3
Yes
If forwarding cannot resolve a data hazard, the pipeline can be stalled.
Two actions must be completed before a beq‘s branch can be taken, actions that take time. Obviously, one is to determine whether the beq‘s two source registers’ values are equal. The other is to compute beq‘s target address.
The action of computing the beq‘s target address can be done earlier, in the ID stage rather than the EX stage. That action means the target address will be computed for all instructions, not just beq instructions. A problem that may occur with such computing for all instructions is (no problem)
For beq, determining if the two source registers’ values are equal is done in an earlier stage than EX using XOR gates.
According to MIPS convention, the term interrupt refers to an unscheduled event caused by an external source. True
Exception handling is not an essential feature of processor’s control unit. False
When an exception occurs in MIPS, the processor first saves the address of the offending instruction in the EPC.
In MIPS, the Cause register stores the cause of an exception and communicates that information to the operating system for exception handling.
For a vectored interrupt, the cause of an exception determines the address that control is transferred to.
