PIC Microcontroller: Operation, Architecture, and Programming

Posted on Dec 5, 2024 in Computers

Modes of Operation

The PIC microcontroller operates in four modes, depending on the external oscillator:

  • RC (Resistor-Capacitor): Low-cost, but with poor stability. Frequency depends on the resistor and capacitor values.
  • HS (High Speed): Operates at 4 to 10 MHz, using a quartz crystal or ceramic resonator.
  • XT (Crystal): Lower frequencies than HS, offering higher accuracy.
  • LP (Low Power): Uses a quartz crystal or ceramic resonator, providing low power consumption at low frequencies (35-200 kHz).

Multiplexer Function

The PIC’s RA4 and RB0 pins have multiplexed functions:

  • RA4: Multiplexes the T0CKI input for Timer0, which receives an external frequency.
  • RB0: Multiplexes the external interrupt input function.

9k =

Open Drain Mode

The RA4 pin operates in open drain mode, meaning it lacks a pull-up resistor, achieving a high-impedance state.

Operating Frequency

Operating frequency determines instruction execution speed and power consumption. For example, a PIC running at 10 MHz has a 400 ns instruction cycle (4 clock periods per instruction). Most instructions execute in one cycle, except jumps, which take two.

Pipeline/Segmentation

The PIC uses a two-stage pipeline for instruction processing:

  • Q1: Program counter increment.
  • Q2-Q3: Instruction decode and execution.
  • Q4: Fetch and load the next instruction into the instruction register.

Harvard Architecture

The PIC’s Harvard architecture allows independent and simultaneous access to data and program memory, with appropriate word lengths and bus sizes, and efficient bank management.

Orthogonality

Any instruction can use any architectural element as a source or destination.

Program Memory

The 16F84 has 1KB of Flash program memory, organized in 14-bit words. It’s read-only. The RESET vector is at 0000h, and the interrupt vector is at 0004h. User memory starts at 0005h.

PCLATH Register

PCLATH provides indirect access to the upper bits of the program counter for certain instructions.

Hardware Stack

The hardware stack is an 8-level deep LIFO (Last-In, First-Out) structure for nested subroutines.

RAM Data Memory Addressing

RAM stores Special Function Registers (SFRs) and General Purpose Registers (GPRs). It’s divided into two 128-byte banks (0 and 1). The 16F84 uses the first 80 locations of each bank. The first 12 are SFRs, and the remaining 68 are GPRs. Locations 07h and 87h are not operational. After RESET, Bank 0 is selected (RP0 = 0).

Addressing Modes

The PIC has three addressing modes:

  • Immediate: Data is included in the instruction’s opcode.
  • Direct: Data is accessed using a 7-bit address in the opcode.
  • Indirect: Data is accessed through the INDF register or during EEPROM access.

Status Register

The Status Register (03h and 83h) indicates ALU operation results, reset and sleep states, and RAM bank selection. Its bits include:

  • C: Carry flag.
  • DC: Digit carry flag.
  • Z: Zero flag.
  • PD: Power-down bit.
  • TO: Time-out bit.
  • RP1, RP0: Bank select bits.
  • IRP: Indirect bank select bit (not used).

2Q ==

TMR0 Timer/Counter

TMR0 is an 8-bit timer/counter. It can count external events on RA4/T0CKI or time instruction cycles. Overflow at FFh triggers an interrupt. The OPTION_REG register configures its mode. A prescaler can be applied.

Timer = 4 * Tosc * (256 – TMR0 Value) * (Prescaler Value)

TMR0 is located at address 01h in Bank 0.

Watchdog Timer (WDT)

The WDT prevents program hangs by resetting the system if the program doesn’t reset it periodically.

OPTION_REG Register

OPTION_REG (81h) controls TMR0 and the prescaler. Its bits include:

  • RBPU: Port B pull-up enable.
  • INTEDG: Interrupt edge select.
  • T0CS: TMR0 clock source select.
  • T0SE: TMR0 edge select.
  • PSA: Prescaler assignment bit.
  • PS2, PS1, PS0: Prescaler rate select bits.

2Q ==

Pull-up Resistors

Pull-up resistors can be enabled for Port B by setting RBPU to 0 in OPTION_REG.

Port A

RA0-RA3 support TTL input and CMOS output levels. RA4/T0CKI has a Schmitt trigger for noise immunity and is open drain.

Port B

RB4-RB7 can generate interrupts on state changes. RB6 is used for program memory paging.

Setting Port A and B as Inputs/Outputs

Example code:

Bsf STATUS, 5
Movlw B'01111111'
Movwf PORTA
Movlw B'00010000'
Movwf PORTB

TRIS Value After RESET

After RESET, TRIS registers are set to 1, configuring ports as inputs.

Configuration Word

The Configuration Word (2007h) is set during programming and controls features like code protection, power-up timer, WDT, and oscillator selection.

Z

EEPROM Data

The PIC has 64 bytes of EEPROM. It’s accessed using four registers:

  • EEDATA: Data register.
  • EEADR: Address register.
  • EECON1, EECON2: Control registers.

9k =

Z

Interrupt Vector

An interrupt saves the current address on the stack and jumps to the interrupt vector (0004h), which leads to the Interrupt Service Routine (ISR).

RETFIE Instruction

The retfie instruction returns from an ISR and re-enables the Global Interrupt Enable (GIE) bit.

Interrupts

Interrupts asynchronously divert program flow. The PIC has four interrupt sources:

  • RB0/INT pin activation.
  • TMR0 overflow.
  • Change on RB1-RB7 pins.
  • EEPROM write completion.

Interrupt Phases

Interrupt handling involves these phases:

  • Interrupt request and enabling.
  • Disabling GIE.
  • Saving PC to the stack.
  • Loading the interrupt vector.
  • Identifying the interrupt source.
  • Executing the ISR.
  • Clearing interrupt flags.
  • Returning from the ISR and re-enabling GIE.

EEPROM Read/Write Processes

Reading involves setting EEADR and the RD bit in EECON1. Writing involves setting EEADR, EEDATA, and the WR bit in EECON1, using EECON2 for control.

INTCON Register

INTCON controls interrupt settings.

9k =

RESET Actions and Causes

RESET initializes the PIC and sets registers to default values. It can be caused by power-on, MCLR pin activation, or WDT overflow.

Brown-out Reset

A brown-out reset occurs when Vdd drops below a threshold. External circuitry can be used to ensure a proper reset.

Sleep Mode

Sleep mode minimizes power consumption. It’s entered using the SLEEP instruction. The PIC can be woken up by MCLR, WDT overflow, or an interrupt (except TMR0).

PWRT and OST

PWRT provides a delay after power-on. OST provides a delay for oscillator stabilization.

Jump Instruction

Jump instructions take two cycles due to the pipeline. They use a 13-bit address.

MOVLW Instruction Cycles

movlw (move literal to w) takes one cycle.

9k =

INCF Instruction

incf increments a register, storing the result in w or the original register.

2Q ==

CCP Module

The CCP module provides capture, compare, and PWM functions.

Program Execution Time Calculation

Example calculation for a 100-instruction program with 10 jumps at 4 MHz and a prescaler of 1/8.

TMR0 Value Calculation

Example calculation for a desired delay with a given prescaler and frequency.

2Q ==

LED Blinking Example

Example calculation for blinking an LED connected to RB7 with a specific frequency.