SAP-1 Architecture, Microprocessors, and Computer Organization
1. SAP-1 Architecture
1.1. Overview
The Simple-As-Possible (SAP)-1 computer, explained by Albert Paul Malvino, is a basic microprocessor model. It demonstrates fundamental microprocessor operations, memory interaction, and input/output processes. Its instruction set is intentionally limited and straightforward.
1.2. Components
1.2.1. Program Counter (PC)
Counts from 0000 to 1111, signaling the memory address of the next instruction.
1.2.2. Inputs and Memory Address Register (MAR)
During execution, the PC’s address is transferred to the MAR.
1.2.3. RAM
Stores program code and data. During execution, it receives 4-bit addresses from the MAR and performs read operations, placing data on the W bus. It’s asynchronous, meaning data is available immediately upon valid address and control signal.
1.2.4. Instruction Register (IR)
Holds the current instruction (OPCODE + ADDRESS).
1.2.5. Controller-Sequencer
Generates control signals for each block, ensuring sequential operation synchronized by the CLK signal. A 12-bit control word dictates register reactions to the next CLK edge.
1.2.6. Accumulator
An 8-bit register storing intermediate results. It’s an operand in ADD, SUB, and OUT instructions.
1.2.7. Adder/Subtractor
A 2’s complement adder/subtractor. It’s asynchronous, meaning its contents change immediately with input changes.
1.2.8. B-Register
An 8-bit register holding the second operand for mathematical operations (the first is the accumulator).
1.2.9. Output Register
Stores the output of the OUT instruction.
1.2.10. Binary Display
Eight LEDs displaying the output register’s contents. It’s the SAP-1’s output device.
2. Microprocessors
2.1. Definition
A microprocessor, the CPU of a computer, executes instructions and manages system operations. It’s used in various devices, from PCs to smartphones and embedded systems.
2.2. Main Functions
- Data Processing: Performs arithmetic and logical operations based on program instructions.
- Control Operations: Sends control signals, managing component functions and communication between memory and I/O devices.
- Data Storage and Transfer: Manages data transfer between memory and I/O devices.
3. Addressing Modes
Addressing modes define how the CPU accesses data. The instruction STA 2000H uses direct addressing because the address 2000H is explicitly within the instruction. STA (Store Accumulator) stores the accumulator’s contents at 2000H.
4. 8085 Registers
- General-Purpose Registers (B, C, D, E, H, L): 8-bit registers for temporary data storage, combinable into 16-bit registers.
- Accumulator (A): Stores intermediate results.
- Flag Register: Contains status flags (Sign, Zero, Auxiliary Carry, Parity, Carry).
- Program Counter (PC): 16-bit register holding the next instruction’s address.
- Stack Pointer (SP): 16-bit register pointing to the stack top.
- Instruction Register: Holds the current instruction’s opcode.
5. Micro Operations
Micro operations are basic data manipulation operations within the CPU, forming the basis of machine-level instructions.
6. Control Unit Types
6.1. Hardwired Control Unit
- Faster but difficult to modify.
- Costlier and handles fewer, simpler instructions.
- Used in RISC architectures.
6.2. Microprogrammed Control Unit
- Slower but easier to modify.
- Less costly and handles complex instructions.
- Used in CISC architectures.
7. Direct Memory Access (DMA)
DMA allows peripherals to access RAM directly, bypassing the CPU. This improves performance, CPU utilization, reduces latency and interrupt overhead, and supports high-speed transfers.
8. Memory Address Map
A memory address map defines memory allocation for data and devices. It specifies regions, access control, peripheral mapping, segmentation, and aids efficient memory management.
9. Data Dependency in Pipelining
Data dependency occurs when instructions rely on previous results. Types include:
- Read After Write (RAW): An instruction reads a value not yet written.
- Write After Read (WAR): An instruction writes before a previous read.
- Write After Write (WAW): Two instructions write to the same location.
These dependencies cause stalls, impacting pipeline efficiency. Solutions include instruction reordering, forwarding, and pipeline stalls.