SAP 1 Computer Architecture & Instruction Formats

Posted on Sep 29, 2024 in Computers

SAP 1 Computer: Architecture and Comparison with SAP 2

SAP (Simple As Possible) computers are basic models used to illustrate computer architecture. SAP 1 and SAP 2 are educational tools that demonstrate the fundamentals of computer operation. SAP 1 has a simple design, while SAP 2 offers greater complexity and functionality.

Components of SAP 1 Computer

  1. Input Device (Switches or Keypad): Provides instructions and data (in binary/machine code) to the computer.
  2. Program Counter (PC): A 4-bit register holding the address of the next instruction. It increments after each cycle to fetch the next instruction from memory.
  3. Memory Address Register (MAR): A 4-bit register holding the memory address for data/instruction fetching or writing.
  4. Memory: 16×8 bit RAM storing instructions and data. The 16 locations are addressed by the MAR.
  5. Instruction Register (IR): Stores the current instruction, holding the opcode that controls execution flow.
  6. Control Unit: Decodes the instruction in the IR and generates signals to control computer parts (memory read/write, ALU operations, etc.).
  7. Accumulator (A Register): An 8-bit register holding results of ALU’s arithmetic and logic operations.
  8. B Register: An 8-bit register serving as the second operand for ALU operations; temporarily stores data.
  9. Arithmetic Logic Unit (ALU): Performs arithmetic (addition) and logical operations. In SAP 1, it only supports addition between the accumulator and B register.
  10. Output Register: Stores the final computation result, displayed on output devices (LED or 7-segment display).

Instruction Format of a Basic Computer and RISC vs. CISC

Instruction Format

The instruction format defines the structure of bits within a machine instruction processed by the CPU. It typically includes:

  1. Opcode (Operation Code): Specifies the operation to be performed by the CPU. The number of bits determines the possible operations.
  2. Address/Operand Fields: Specify memory locations of operands or registers to be used. Operands might be embedded directly (immediate mode).
  3. Mode Field: Indicates how operands are interpreted (register, memory, or immediate value).

Instruction structure varies depending on the computer’s architecture, classified as RISC or CISC.

Restoring Division Algorithm for Fixed Point Binary Division

This method involves repeatedly subtracting the divisor from the dividend, shifting the quotient and remainder left. If the remainder becomes negative, we restore it by adding back the divisor and adjust the quotient.

Steps:

  1. Initialize Registers:
    • Dividend in the Quotient register.
    • Remainder register initialized to 0.
    • Divisor in a separate register.
    • Register length for Quotient and Remainder is typically one bit more than the binary number’s length.
  2. Shift Left both Remainder and Quotient.
  3. Subtract the divisor from the Remainder.
  4. If the result is positive or zero:
    • Set the least significant bit of the Quotient to 1.
    • Keep the Remainder.
  5. If the result is negative:
    • Set the least significant bit of the Quotient to 0.
    • Restore the Remainder by adding back the divisor.
  6. Repeat steps 2-5 for the number of bits in the quotient (or register size).

After the iterations, the Quotient register holds the quotient, and the Remainder register holds the remainder.