Semiconductor Manufacturing: From Crystal to Chip

Posted on Nov 24, 2024 in Technology

Chapter 1: Development of a Semiconductor Industry

Early Stages

The electronic industry’s foundation lies in the vacuum tube and early silicon use for signal transmission before World War II. The University of Pennsylvania developed the first electronic computer, ENIAC, during World War II.

The Transistor

William Shockley, John Bardeen, and Walter Brattain invented the solid-state transistor at Bell Telephone Laboratories on December 16, 1947. The semiconductor industry experienced rapid growth in the 1950s, commercializing transistor technology, with many pioneers working in Northern California’s Silicon Valley.

Circuit Integration

Jack Kilby at Texas Instruments and Robert Noyce at Fairchild Semiconductor independently co-invented the first integrated circuit (IC) in 1959. An IC combines multiple electronic components on a silicon substrate.

Circuit integration eras:

  • Small Scale Integration (SSI): 2-50 components
  • Medium Scale Integration (MSI): 50-5k components
  • Large Scale Integration (LSI): 5k-100k components
  • Very Large Scale Integration (VLSI): 100k-1M components
  • Ultra Large Scale Integration (ULSI): > 1M components

IC Fabrication

Chips (or die) are fabricated on thin silicon slices called wafers (or substrates). Wafer fabrication occurs in facilities known as wafer fabs, or simply fabs.

Five stages of IC fabrication:

  • Wafer Preparation: Silicon purification and wafer creation.
  • Wafer Fabrication: Microchip fabrication by merchant chip suppliers, captive chip producers, fabless companies, or foundries.
  • Wafer Test: Electrical testing of each die.
  • Assembly and Packaging: Packaging of individual die.
  • Final Test: Electrical testing of packaged ICs.

Key semiconductor trends:

  • Increased chip performance through reduced critical dimensions (CD), more components per chip (Moore’s Law), and reduced power consumption.
  • Increased chip reliability.
  • Reduced chip price.

The Electronic Era

  • 1950s: Development of various transistor technologies and the silicon age.
  • 1960s: IC process development and emergence of chip manufacturers.
  • 1970s: Medium-scale integration, increased competition, microprocessor development, and equipment technology advancements.
  • 1980s: Wafer fab automation, improved efficiency, and product quality.
  • 1990s: ULSI era and volume production of sub-micron ICs.

Career Paths

Semiconductor manufacturing offers diverse career paths, including technician, engineer, and management roles.

Chapter 2: Characteristics of Semiconductor Materials

Atomic Structure

The atomic model consists of neutral neutrons, positively charged protons in the nucleus, and negatively charged electrons orbiting the nucleus. Valence shell electrons influence the atom’s chemical and physical properties. Ions form when atoms gain or lose electrons.

The Periodic Table

The periodic table lists all known elements. The group number indicates the number of valence electrons. We focus on groups IA through VIIIA.

Ionic bonds form when electrons transfer between atoms. Unstable atoms (e.g., group VIIIA) readily form ionic bonds. Covalent bonds involve shared electrons.

Classifying Materials

Three classes of materials:

  • Conductors: Low resistance to current flow (e.g., copper).
  • Insulators: High resistance to current flow.
  • Semiconductors: Can function as conductors or insulators.

Capacitance is the charge storage on two conductive plates separated by a dielectric. The dielectric constant measures the insulation quality.

Silicon

Silicon, an elemental semiconductor, has four valence electrons. It’s refined from silica to make wafers. Pure silicon is intrinsic. Silicon atoms form covalent bonds in a crystal structure.

Reasons for silicon replacing germanium:

  • Abundance
  • Higher melting point
  • Wider temperature range
  • Natural silicon dioxide growth

Silicon dioxide (SiO2) is a stable insulator and chemical barrier. Growing thin SiO2 is crucial for MOS devices.

Doping enhances conductivity. Common dopants are trivalent, p-type Group IIIA (boron) and pentavalent, n-type Group VA (phosphorus, arsenic, antimony).

The pn junction enables silicon’s semiconductor function.

Alternative Semiconductor Materials

Compound semiconductors (III-V compounds like gallium arsenide – GaAs) and II-VI compounds are alternatives.

GaAs offers greater electron mobility and radiation hardness but lacks a natural oxide.

Chapter 3: Device Technologies

Circuit Types

Analog circuits have continuous electrical data. Digital circuits operate with distinct high and low voltage levels.

Passive Component Structures

Passive components (resistors, capacitors) conduct current regardless of connection. IC resistors can have parasitic resistance. IC capacitors can have unintentional capacitance.

Active Component Structures

Active components (diodes, transistors) control current flow. PN junction diodes have a depletion region and barrier voltage. Bias voltage can be reverse or forward.

Bipolar junction transistors (BJTs) have three electrodes, two pn junctions, and amplify current. Schottky diodes improve BJT circuit speed and efficiency.

Field-effect transistors (FETs) are compact and efficient. MOSFETs have a gate oxide. nMOS and pMOS are defined by majority carriers. CMOS combines nMOS and pMOS. BiCMOS combines CMOS and bipolar technologies.

FETs can be enhancement or depletion mode, based on channel doping.

Latchup in CMOS Devices

Parasitic transistors can cause latchup. Epitaxial layers and isolation barriers control latchup.

Integrated Circuit Products

Linear ICs handle analog circuits. Digital ICs operate with binary data.

Chapter 4: Silicon and Wafer Preparation

Semiconductor-Grade Silicon

Semiconductor-grade silicon (SGS), or electronic-grade silicon, is highly refined using the Siemens process.

Crystal Structure

Crystals have ordered 3D patterns. Unit cells are the fundamental repeating units. Silicon has a face-centered cubic diamond structure. Polycrystals have non-regular arrangements, while monocrystals have neatly arranged unit cells.

Crystal Orientation

Miller indices describe unit cell orientation. Common planes are (100), (110), and (111). (100) is common for MOS, while (111) is common for bipolar devices.

Monocrystal Silicon Growth

Czochralski (CZ) method grows ingots with controlled orientation and doping. Key parameters are pull rate and rotation. Magnetic CZ enhances homogeneity. Dopants are added to the melt. Float-zone method achieves high purity.

Larger diameter ingots (300-mm) offer cost benefits.

Crystal Defects in Silicon

Crystal defects interrupt unit cell repetition. Defect density is defects per cm2.

Defect types:

  • Point defects: Vacancies, interstitials, Frenkel defects.
  • Dislocations: Stacking faults.
  • Gross defects: Related to crystal structure.

Wafer Preparation

Ingots undergo shaping (end removal, grinding, flat/notch), slicing, lapping, etching, polishing, cleaning, evaluation, and packaging.

Quality Measures

  • Physical dimensions
  • Flatness
  • Microroughness
  • Oxygen content
  • Crystal defects
  • Particles
  • Bulk resistivity

Epitaxial Layer

An epitaxial (epi) layer, grown on the surface, controls doping and minimizes latch-up.

Chapter 5: Chemicals in Semiconductor Fabrication

States of Matter

Matter exists as solid, liquid, gas, and plasma.

Properties of Materials

  • Temperature
  • Pressure and vacuum
  • Condensation and vaporization
  • Vapor pressure
  • Sublimation and deposition
  • Density
  • Surface tension
  • Thermal expansion and stress

Process Chemicals

Chemical solutions have solvents and solutes. Acids yield hydronium ions. Bases yield hydroxide ions. The pH scale (0-14) measures acidity/basicity.

Bulk chemical distribution (BCD) and point-of-use (POU) systems deliver chemicals. Gases are bulk (oxygen, nitrogen, hydrogen, helium, argon) or specialty (process) gases.

Specialty gases are transported in cylinders. Gas purges flush residual gas. Gas sticks control incoming gas. Specialty gases can be hydrides, fluorinated compounds, or acid gases.

Chapter 6: Contamination Control in Wafer Fabs

Introduction

Modern fabs are cleanrooms.

Types of Contamination

  • Particles: Killer defects if > half the minimum feature size.
  • Metallic impurities: Mobile ionic contaminants (MICs).
  • Organic contamination
  • Native oxides
  • Electrostatic discharge (ESD)

Sources and Control of Contamination

Sources:

  • Air: Classified by particle size and density.
  • Humans: Wear garments and follow protocols.
  • Facility: Ballroom or bay and chase design. Laminar airflow and filtering. ESD control via static-dissipative materials, grounding, and ionization.
  • Ultrapure deionized (DI) water: Filtered, zeta potential control, UV sterilization.
  • Process chemicals: Filtered.
  • Process gases: Filtered.
  • Production equipment
  • Workstation design: Bulkhead equipment, robotic wafer handlers, minienvironments.

Wafer Wet Cleaning

RCA clean (SC-1 and SC-2) is the standard. SC-1 removes particles and organics. SC-2 removes metals. Diluted chemistries, piranha clean, and HF last are used.

Megasonics, spray cleaning, and scrubbing are common. Rinsing and drying methods vary.

Dry cleaning alternatives include plasma, ozone, and cryogenic aerosol cleaning.

Chapter 7: Metrology and Defect Inspection

IC Metrology

Metrology determines physical and electrical properties. In-process data is collected on monitor wafers. Yield measures good parts produced.

Quality Measures

Film thickness is measured for opaque (four-point probe, contour maps) and transparent (ellipsometry, reflectometry, X-ray, photoacoustic) films.

Film stress is measured via radius of curvature changes. Refractive index variations indicate contamination.

Dopant concentration is measured with four-point probe, thermal-wave, and spreading resistance probe.

Microscopes use brightfield and darkfield detection. Light scattering detects particles.

Critical dimensions (CDs) are measured with SEM. Surface profilers measure conformal step coverage. Overlay registration measures pattern alignment.

Capacitance-voltage (C-V) tests verify gate structure quality.

Analytical Equipment

  • Secondary-ion mass spectrometry (SIMS): Analyzes surface composition.
  • Atomic force microscope (AFM): Creates 3D surface maps.
  • Auger electron spectroscopy (AES): Measures surface composition.
  • X-ray photoelectron spectroscopy (XPS): Identifies surface chemical species.
  • Transmission electron microscopy (TEM): Analyzes small features.
  • Energy-dispersive spectrometer (EDX): Identifies elements.
  • Focused ion beam (FIB): Carves cross-sections for analysis.

Chapter 8: Gas Control in Process Chambers

Process chambers are controlled vacuum environments, often in cluster tools.

Vacuum

Vacuum ranges: low, medium, high, ultrahigh (UHV). Mean free path increases with lower pressure.

Vacuum Pumps

Roughing pumps (dry mechanical, blower) achieve low to medium vacuum. High vacuum pumps (turbomolecular, cryopump) achieve high to UHV.

Process Chamber Gas Flow

Mass flow controllers (MFCs) control gas flow. Residual gas analyzers (RGAs) identify remaining gases.

Plasma

Plasma is energized ionized gas. RF power creates glow discharge.

Chapter 9: IC Fabrication Process Overview

CMOS Process Flow

Major process areas:

  • Diffusion: High-temperature processing and depositions.
  • Photolithography: Pattern transfer.
  • Etch: Pattern creation.
  • Ion implanter: Doping.
  • Thin films: Dielectric and metal deposition.
  • Polish: Wafer planarization.

CMOS Manufacturing Steps

  • Twin well process
  • Shallow trench isolation
  • Poly gate structure
  • Lightly doped drain implant
  • Sidewall spacer formation
  • Source/drain implant
  • Contact formation
  • Local interconnect (LI)
  • Via-1 and plug-1 formation
  • Metal-1 interconnect
  • Via-2 and plug-2 formation
  • Metal-2 interconnect
  • Metal-3 to pad etch and alloy
  • Parametric testing

Chapter 10: Oxidation

Introduction

Oxide layers can be grown (using oxygen) or deposited (reacting silicon with oxygen).

Oxide Film

SiO2 has a tetrahedron structure. It’s used for protection, isolation, gate dielectric, doping barrier, and interlayer dielectric.

Thermal Oxidation Growth

Thermal oxide grows via dry or wet oxidation. Wet oxidation is faster but less dense. Silicon is consumed during growth (0.46 of oxide thickness).

Growth is limited by oxygen diffusion. Chlorine neutralizes interface charge.

Oxidation has linear (reaction-rate controlled) and parabolic (diffusion controlled) stages.

Factors affecting growth: doping, crystal orientation, pressure, plasma.

Selective oxidation isolates devices. LOCOS is traditional, STI is preferred for advanced processes.

Furnace Equipment

Horizontal, vertical, and rapid thermal processor (RTP) furnaces exist. Vertical furnaces offer advantages.

Horizontal versus Vertical Furnaces

Vertical furnaces have smaller footprints, parallel processing, and better gas flow. Key control systems: chamber, wafer transfer, gas distribution, exhaust, temperature.

Furnace materials: quartzware, silicon carbide. Multiple heat zones and thermocouples control temperature. Typical ramp rate: 10°C/minute.

Fast ramp vertical furnaces achieve 100°C/minute. RTPs heat single wafers rapidly (400-1300°C). Advantages: reduced thermal budget, minimized dopant movement.

Oxidation Process

Process type depends on thickness and properties. Cleaning is crucial. Recipes control parameters.

Chapter 11: Deposition

Film Deposition

Multilevel metallization uses metal and dielectric layers. Aluminum is traditional, copper is newer. Interlayer dielectric (ILD) is typically SiO2.

Thin film properties: step coverage, gap fill, uniformity, purity, density, stoichiometry, adhesion.

Aspect ratio: depth/width. High aspect ratio gap fill is crucial.

Film growth stages: nucleation, coalescence, continuous film. Films can be amorphous, polycrystalline, or single crystalline.

Deposition types: chemical (CVD, plating), physical (sputtering, evaporation, spin-on).

Chemical Vapor Deposition

CVD deposits films via gas reactions. Reactions: pyrolysis, photolysis, reduction, oxidation, redox.

CVD steps: gas transport, precursor formation, wafer arrival, adsorption, diffusion, reactions, by-product removal.

Processes can be mass-transport or reaction-rate limited.

Doped SiO2 forms PSG, BPSG, FSG.

CVD Deposition Systems

CVD reactors: APCVD, LPCVD, PECVD, HDPCVD. HDPCVD is best for gap fill.

Dielectrics and Performance

Low-k dielectrics reduce capacitance. High-k dielectrics are used in DRAMs and gate oxides.

Spin-On-Dielectrics

Spin-on techniques apply some low-k dielectrics.

Epitaxy

Epitaxy grows single-crystal layers. Methods: vapor-phase, MOCVD, MBE.

Chapter 12: Metallization

Introduction

Metallization deposits conductive metal.

Types of Metals

Metal requirements: conductivity, adhesion, deposition ease, patterning, planarization, reliability, corrosion resistance, stress resistance.

Metals used: aluminum, aluminum-copper alloys, copper, barrier metals, silicides, metal plugs.

Copper offers lower resistivity, power consumption, better density, electromigration resistance.

Barrier metals prevent intermixing. Silicides are thermally stable and have low resistivity. Salicides align source, drain, and gate. Metal plugs fill vias.

Metal Deposition Systems

Sputtering (PVD) replaced evaporation. Ionized metal plasma PVD improves step coverage. Metal CVD deposits tungsten plugs and copper seed layers. Copper electroplating is used in dual damascene.

Metallization Schemes

Traditional (aluminum) and copper (dual damascene) schemes exist.

Chapter 13: Photolithography (Vapor Prime to Soft Bake)

Introduction

Photolithography creates patterns using photoresist and light. Resolution and alignment are critical.

Photolithography Processes

Negative resists create negative images. Positive resists create positive images. Sub-micron fabs use positive resist.

Eight Basic Steps of Photolithography

  1. Vapor prime
  2. Spin coat
  3. Soft bake
  4. Alignment and exposure
  5. Post-exposure bake (PEB)
  6. Develop
  7. Hard bake
  8. Develop inspect

Vapor Prime

Wafers are cleaned, dehydrated, and primed with HMDS for adhesion.

Spin Coat

Photoresist is applied by spinning. Resist properties: resolution, contrast, sensitivity, viscosity, adhesion, etch resistance, surface tension, storage, contamination.

I-line resists contain resin, sensitizer, and solvent. Deep UV resists are used for smaller features. Chemically amplified resists require PEB.

Spin coating steps: dispense, spin-up, spin-off, evaporation.

Soft Bake

Soft bake removes solvent and improves adhesion. Vacuum hot plates are preferred.

Chapter 14: Photolithography (Alignment and Exposure)

Introduction

Optical lithography uses UV light, optics, reticles, alignment, and photoresist.

Optical Lithography

UV sources: mercury arc lamps (g-line, h-line, i-line), excimer lasers (KrF, ArF, F2).

Optics use reflection and refraction. Lens materials: glass, fused silica, CaF2.

Diffraction is light bending. Numerical aperture (NA) measures diffracted light collection. Antireflective coatings reduce reflectivity.

Resolution (R) = (kλ)/NA. Depth of focus (DOF) = λ/2(NA)2. Planar surfaces are needed for large DOF.

Photolithography Equipment

Contact aligners, proximity aligners, scanners, steppers, and step-and-scan systems exist. Step-and-scan systems are common for advanced processes.

Reticles contain patterns. Reduction ratios (5:1, 4:1) are common. Reticles are fabricated with e-beam lithography. Pellicles protect reticles.

Enhancement techniques: phase-shift masks, optical proximity correction, off-axis illumination, print bias.

Alignment marks and systems ensure proper alignment.

Mix and Match

Different equipment is used for different layers.

Chapter 15: Photolithography: Photoresist Development and Advanced Lithography

Introduction

This chapter covers PEB, develop, hard bake, inspect, and advanced lithography.

Post-Exposure Bake

PEB is used for chemically amplified resists and to reduce standing waves.

Develop

Developers dissolve soluble resist regions. TMAH is common for positive resists. Development techniques: continuous spray, puddle.

Critical parameters: temperature, time, volume, chuck, normality, rinse, exhaust.

Hard Bake

Hard bake removes solvent and hardens resist.

Develop Inspect

Inspection detects resist defects.

Advanced Lithography

Subwavelength lithography patterns features smaller than the wavelength.

Next-generation lithography:

  • Extreme UV (EUV)
  • SCALPEL
  • Ion projection lithography (IPL)
  • X-ray

Advanced resist processing includes top-surface imaging.

Chapter 16: Etch

Introduction

Etch selectively removes material. Dry etch uses plasma. Wet etch uses chemicals.

Etch Parameters

  • Etch rate
  • Etch profile: isotropic (undercutting), anisotropic (directional).
  • Etch bias
  • Selectivity
  • Uniformity
  • Residues
  • Polymer formation
  • Plasma-induced damage
  • Particle contamination

Dry Etch

Dry etch is anisotropic. Endpoint control is crucial. Mechanisms: physical, chemical.

Plasma Etch Reactors

  • Barrel
  • Parallel plate (planar)
  • Downstream
  • Triode planar
  • Ion beam milling
  • Reactive ion etch (RIE)
  • High-density plasma: ECR, ICP, DPS, MERIE

Endpoint detection uses optical emission spectroscopy.

Dry Etch Applications

  • Dielectric: Fluorocarbon chemistry.
  • Silicon: Chlorine or bromine chemistry.
  • Metal: Chlorine chemistry.

Wet Etch

Wet etch is less common. Wet strips remove resist or nitride.

Photoresist Removal

Dry plasma ashing with oxygen is the dominant method. Downstream reactors minimize damage.

Chapter 17: Ion Implant

Introduction

Ion implantation dopes wafers. Thermal diffusion is an older method.

Diffusion

Diffusion is movement from high to low concentration. Steps: predeposition, drive-in, activation.

Ion Implantation

Ion implantation is a physical process. Parameters: dose (ions/cm2), range (distance).

Beam current controls dose. Energy controls range.

Ion Implanters

Subsystems: ion source, extraction/analyzer, acceleration column, scanning system, process chamber.

Implanter types: high-current/energy, low-energy.

Beam blow-up is controlled by space charge neutralization. Neutral beam traps remove residual gas.

Scanning types: electrostatic, mechanical, hybrid, parallel.

Thermal anneal (RTA) activates ions. Channeling is controlled by tilt, screen oxide, or preamorphization.

Ion Implant Trends in Process Integration

  • Deep buried layers
  • Retrograde wells
  • Punchthrough stoppers
  • Threshold voltage adjustment
  • Lightly doped drain (LDD)
  • Source/drain implants
  • Polysilicon gate
  • Trench capacitor
  • Ultrashallow junctions
  • Silicon-on-insulator (SOI): SIMOX

Chapter 18: Chemical Mechanical Planarization

Introduction

Topography describes nonplanar surfaces. CMP planarizes wafers.

Traditional Planarization

  • Etchback
  • Glass reflow
  • Spin-on films

Chemical Mechanical Planarization

CMP is global planarization. It uses a polishing pad, slurry, and rotary/orbital motion.

CMP reduces WIWNU and WTWNU.

Advantages: global planarization, multimaterial capability.

Oxide CMP follows Cook’s theory. Metal CMP involves oxidation and abrasion.

Pattern density effects cause erosion and dishing.

Slurries vary by material. Pads are often polyurethane and require conditioning.

Selectivity, overburden, and endpoint detection (motor current, optical) are important.

CMP cleaning is dry-in/dry-out with scrubbing.

CMP Applications

  • STI oxide polish
  • LI oxide polish
  • LI tungsten polish
  • ILD oxide polish
  • Tungsten plug polish
  • Dual-damascene copper polish

CMP Quality Measures

Microscratching is a concern.

Chapter 19: Wafer Test

Introduction

Wafer test measures electrical parameters.

Wafer Test

In-line parametric test (DC test) is done early. Wafer sort (probe) tests each die. Tests: DC, output checks, functional.

Yield models (Poisson, Murphy, Seed) predict yield.

Chapter 20: Assembly and Packaging

Introduction

Assembly separates and attaches die. Packaging protects and provides interconnections.

Traditional Assembly

Steps: backgrind, die separation, die attach (epoxy, eutectic, glass frit), wire bonding (thermocompression, ultrasonic, thermosonic).

Traditional Packaging

Plastic and ceramic (refractory, CERDIP) packaging exist.

Advanced Assembly and Packaging

  • Flip chip
  • Ball grid array (BGA)
  • Chip on board (COB)
  • Tape automated bonding (TAB)
  • Multichip modules (MCM)
  • Chip scale packaging (CSP)
  • Wafer-level packaging