Serial Peripheral Interface (SPI) Bus: A Comprehensive Look

Posted on Dec 14, 2024 in Computers

Definition of Serial Communication

In telecommunications and computing, serial communication is the process of sequentially sending data one bit at a time over a communication channel or computer bus. This contrasts with parallel communication, where all the bits of each symbol (the smallest unit of data transmitted at a time) are sent together.

Serial communication is used in almost all communications and computer networks because the costs of cables and the difficulties of synchronizing parallel communication make it impractical.

Basic Information on the SPI Bus

The Serial Peripheral Interface (SPI) bus was originally developed by Motorola in the late 1980s for its 68000 series microcontrollers. Because of the bus’s simplicity and popularity, many other manufacturers have adopted the standard over the years. Now, you can find a wide variety of components commonly used in embedded systems design. The SPI bus is used primarily between microcontrollers and immediate peripherals. It is commonly found in mobile phones, PDAs, and other mobile devices that communicate data between the CPU, keyboard, screen, and memory chips.

Serial Peripheral Interface (SPI) Bus

The SPI bus is a three-line bus on which 8-bit information packets are transmitted. Each of these three lines carries information between different devices connected to the bus. Each device connected to the bus can act as a transmitter and receiver simultaneously, so this type of serial communication is full-duplex. Three lines transfer the data (one in each direction), and the third line is the clock. Some devices can only be transmitters, and others only receivers; usually, a device that can process data can also receive it.

An example might be an EEPROM memory, which is a device that can transmit and receive information.

Devices connected to the bus are defined as masters and slaves. A master initiates the transfer of information on the bus and generates clock signals and control.

A slave is a device controlled by the master. Each slave on the bus is controlled through a selector line called Slave Select or Chip Select, so a slave is enabled only when this line is selected. Usually, a selection line is dedicated to each slave.

At a certain time, only one master can be on the bus. Any slave device that is not selected must be disabled (put in high impedance) through the selector line (chip select).

The SPI bus employs a simple shift register to transmit information.

In other words, it enables communication between integrated circuits of electronic equipment.

This bus is also sometimes used for data transmission, as its 4-pin configuration (data entry, data output, clock, and chip selector) can easily implement a full-duplex system.

In the market for memory devices, EEPROM (electrically erasable ROM), the SPI bus has experienced a growth spurt lately because it offers advantages in speed and interfacing with microcontrollers over other technologies.

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SPI Bus Hardware

The hardware consists of clock signals, data in, data out, and chip select for each integrated circuit that has to be controlled. Almost any digital device can be controlled with this combination of signals. The devices differ in a predictable number of ways. Some read the data on the rising edge of the clock, and others on the falling edge. Writing is almost always in the opposite direction from the direction of movement of the clock. Some devices have two clocks: one to capture or display data and one for the internal device.

Pros and Cons of the SPI Bus

Advantages

Full-duplex communication
Higher transmission speeds than I²C or SMBus
Flexible protocol that allows absolute control over the bits transmitted
- Not limited to the transfer of 8-bit blocks
- Choice of the size of the bitstream, its meaning, and purpose
Extremely simple hardware implementation
- Consumes less energy than I²C or SMBus because it has less circuitry (including pull-up resistors), and these are simpler
- Arbitration is not required, nor is a fail-response mechanism
- Slave devices use the clock sent by the master; therefore, they do not need their own clock
- It is not required to implement a transceiver (transmitter and receiver); a connected device can be configured to send only, receive only, or both at once
Uses far fewer terminals on each chip/connector than an equivalent parallel interface
At most, a single specific signal for each slave (SS signal); other signals can be shared

Disadvantages

Consumes more terminals on each chip than I²C, even in the 3-wire alternative
Routing is done through specific lines (out-of-band signaling), unlike I²C, where each chip is selected by a 7-bit address sent through the same bus lines
No hardware flow control
No acknowledgment signal. The master may be sending information without any slave connected, and it would not realize anything
It is not easy to have several masters on the bus
Only works at short distances, unlike, for example, RS-232, RS-485, or CAN bus

SPI in Depth

The SPI system, as the name suggests, is a serial communication system between peripherals. It is a low-cost, low-speed system for short-distance communications, for example, between small processors and their peripherals.

It is a full-duplex system, very easy to implement between two hosts. If this system is used for more than two hosts, it begins to lose its advantages, while the bus system, based on the I2C protocol, works better. However, SPI can offer much higher ratios, which may reach the tens of megahertz.

SPI System Interface

The system comprises a master component and one or more slave components. The master is commonly defined as a microcomputer equipped with an SPI clock (SPI clock), and slaves are any integrated circuit receiving the SPI clock from the master. The ASIC (Application-Specific Integrated Circuit) in VTI technology products always work as slave components in master-slave operating mode.

SPI is a synchronous 4-wire serial interface. Data communication is activated by a low signal applied at the Slave Select (SS) or Chip Select (CSB) input. The data are transmitted using three connections:

Connection to the serial data input (MOSI).
The data output (MISO).
Clock signal (SCK).

SPI System Specifications

In the SPI system, there is a Master (for the communication system) and one or more slaves, as we see in these diagrams.

Fig 1. Case of Master with a slave [2]

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Table: Signals SPI system (Signal Name Description)

SCLK Clock

MOSI Master Out – Slave In

MISO Master In – Slave Out

SS Slave select

Fig 2. Case of Master with more than one slave [3]

Communication Between Peripherals

The master generates a clock signal and sends it to the slaves. The slave selection line is used to indicate which slave the master is trying to communicate with.

As you can see, all signals except the slave selection are common to all slaves; therefore, the master must indicate which slave is active during communication.

We can imagine that with more than one or two slaves, the number of master outputs and the number of tracks on the board would be too much to justify the use of this protocol.

SPI uses a pair of parameters called clock polarity (CPOL) and clock phase (CPHA) to determine when the data is valid according to the clock signal. These should be established in both the master and slave devices for communication to work properly. With these parameters, we determine the right sampling time.

We can see an example of the four different ways we can have.

Table: Modes of transmission over SPI

CPOL / CPHA Leading Edge Trailing Edge SPI Mode

0 / 0 Sample, Setup rising, falling 0

0 / 1 Setup, Sample rising, falling 1

1 / 0 Sample, falling Setup, Rising 2

1 / 1 Setup, falling Sample, Rising 3

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Fig 3. SPI Transfer Format with CPHA = 0 [4]

Fig 4. SPI Transfer Format with CPHA = 1 [5]

In this example (Figures 3 and 4), we can see that both the MSB and the LSB can be transmitted first, depending on how the SPI hardware is configured.

SPI Communication Process

Communication between the master and slave functions as follows:

The Master puts the slave select line of the slave with whom it wants to interact low. This indicates to the slave to be prepared to initiate communication.
The master generates the clock signal according to the SPI mode. Both the master and slave transmit one bit per clock cycle.
After a byte, the Master puts the slave select line at a high level.