Symmetric Shared Memory Architecture and Cache Coherence

Posted on Dec 23, 2024 in Computers

Symmetric Shared Memory Architecture

Symmetric Shared Memory (SSM) architecture is a type of multiprocessor architecture where multiple processors share a common memory space and have equal access to the shared memory. In SSM architecture, all processors are connected to the shared memory through a shared bus or interconnect.

Characteristics of Symmetric Memory Architecture

  • Shared Memory: All processors share a common memory space, which allows for efficient communication and data sharing between processors.
  • Symmetric Access: All processors have equal access to the shared memory, and each processor can access any memory location.
  • Shared Bus or Interconnect: Processors are connected to the shared memory through a shared bus or interconnect, which allows for communication between processors.
  • Multiple Processors: Multiple processors are used to increase processing power and improve system performance.

Advantages of Symmetric Memory Architecture

  • Easy to Program: SSM architecture is relatively easy to program, as all processors share a common memory space and can access any memory location.
  • Fast Communication: Communication between processors is fast, as they share a common memory space and can access each other’s data directly.
  • Scalability: SSM architecture can be scaled up to support a large number of processors, making it suitable for high-performance computing applications.
  • Fault Tolerance: SSM architecture can provide fault tolerance, as if one processor fails, the other processors can continue to operate and provide service.

Disadvantages of Symmetric Memory Architecture

  • Limited Scalability: While SSM architecture can be scaled up to support a large number of processors, it can become difficult to manage and maintain as the number of processors increases.
  • Cache Coherence: SSM architecture requires cache coherence protocols to ensure that each processor has a consistent view of the shared memory. This can add complexity and overhead to the system.
  • Bus Contention: As the number of processors increases, bus contention can become a problem, leading to decreased system performance.
  • Cost: SSM architecture can be more expensive than other types of multiprocessor architectures, as it requires a shared memory bus or interconnect and multiple processors.

Types of Symmetric Memory Architecture

  • Uniform Memory Access (UMA): In UMA architecture, all processors have equal access to the shared memory, and memory access times are uniform.
  • Non-Uniform Memory Access (NUMA): In NUMA architecture, processors have different access times to different parts of the shared memory.
  • Cache-Coherent NUMA (ccNUMA): In ccNUMA architecture, a cache coherence protocol is used to ensure that each processor has a consistent view of the shared memory.

Multiprocessor Cache Coherence Problem

In SSM systems, each processor typically has its own private cache to reduce the average memory access time and the load on the shared memory. While caches improve performance, they introduce the problem of cache coherence. Cache coherence refers to the consistency of data stored in local caches of a shared resource.

The Cache Coherence Problem

When multiple processors cache copies of the same memory location, modifications to that location by one processor must be reflected in the caches of all other processors. Otherwise, processors might end up working with stale data, leading to incorrect program execution.

Consider an example where two processors, P1 and P2, both have a cached copy of a memory location X:

  • If P1 updates X, the change must be propagated to P2’s cache.
  • If P2 reads X after P1’s update, it should get the updated value.

Cache Coherence Protocols

To address the cache coherence problem, several protocols have been developed. These protocols ensure that all processors see a consistent view of memory. The two main types of cache coherence protocols are:

Directory-Based Protocols

  • A centralized directory keeps track of the state of each memory block and which caches have copies of that block.
  • When a processor wants to read or write a block, it consults the directory to ensure the operation maintains coherence.
  • Example: Each memory block has a directory entry that records which processors have cached copies and whether the block is in a modified state.

Snooping Protocols

  • Processors monitor a common communication medium (usually a bus) to track the state of memory blocks.
  • When a processor wants to read or write a block, it broadcasts the operation on the bus, and all other processors “snoop” on the bus to ensure coherence.
  • Example: MESI (Modified, Exclusive, Shared, Invalid) protocol, where each cache line can be in one of four states, and processors broadcast operations to maintain coherence.