Understanding 74193 4-Bit Binary Counter Operations
Understanding the 74193 4-Bit Binary Counter
Presetting the Counter
The flip-flops (FFs) within the 74193 counter can be preset to the logical levels present at the parallel data inputs (P3 to P0) by momentarily setting the parallel load input (PL) to LOW. This is an asynchronous preset operation, meaning it overrides the counting process. However, PL will not function if the master reset input (MR) is in its active HIGH state.
Checking the Count
The current count is always available at the outputs Q3 to Q0, where Q0 is the least significant bit (LSB) and Q3 is the most significant bit (MSB).
Checking the End of Counting
These outputs are crucial when connecting two or more 74193 units to create a multi-stage counter with a larger modulus (MOD). In count-up mode, the terminal count-up output (TCu) of the lower-order counter is connected to the count-up input (CPu) of the next higher-order counter. In countdown mode, the terminal count-down output (TCd) of the lower-order counter is connected to the count-down input (CPd) of the next higher-order counter.
Terminal Count-Up (TCu)
TCu, also known as the carry output, is generated using the logic shown in Figure 7(a). TCu will only go LOW when the counter is in the 1111 state and CPu is LOW. It remains HIGH while the counter increments from 0000 to 1110. On the next clock pulse (CP or TPP), the count goes to 1111, but TCu does not go LOW until CPu returns to a LOW state. The subsequent clock pulse on CPu resets the counter to 0000 and causes TCu to return HIGH. This transition of TCu can be used to clock a second 74193 counter for higher counts.
Terminal Count-Down (TCd)
TCd, also known as the borrow output, is generated as shown in Figure 7(b). It is normally HIGH and only goes LOW when the counter has decremented to the 0000 state and CPd is LOW. When the next clock pulse arrives at CPd, it resets the counter to 1111, causing TCd to return HIGH. This transition of TCd can be used to clock a second 74193 counter for lower counts.
Understanding the 74193 4-Bit Binary Counter
Presetting the Counter
The flip-flops (FFs) within the 74193 counter can be preset to the logical levels present at the parallel data inputs (P3 to P0) by momentarily setting the parallel load input (PL) to LOW. This is an asynchronous preset operation, meaning it overrides the counting process. However, PL will not function if the master reset input (MR) is in its active HIGH state.
Checking the Count
The current count is always available at the outputs Q3 to Q0, where Q0 is the least significant bit (LSB) and Q3 is the most significant bit (MSB).
Checking the End of Counting
These outputs are crucial when connecting two or more 74193 units to create a multi-stage counter with a larger modulus (MOD). In count-up mode, the terminal count-up output (TCu) of the lower-order counter is connected to the count-up input (CPu) of the next higher-order counter. In countdown mode, the terminal count-down output (TCd) of the lower-order counter is connected to the count-down input (CPd) of the next higher-order counter.
Terminal Count-Up (TCu)
TCu, also known as the carry output, is generated using the logic shown in Figure 7(a). TCu will only go LOW when the counter is in the 1111 state and CPu is LOW. It remains HIGH while the counter increments from 0000 to 1110. On the next clock pulse (CP or TPP), the count goes to 1111, but TCu does not go LOW until CPu returns to a LOW state. The subsequent clock pulse on CPu resets the counter to 0000 and causes TCu to return HIGH. This transition of TCu can be used to clock a second 74193 counter for higher counts.
Terminal Count-Down (TCd)
TCd, also known as the borrow output, is generated as shown in Figure 7(b). It is normally HIGH and only goes LOW when the counter has decremented to the 0000 state and CPd is LOW. When the next clock pulse arrives at CPd, it resets the counter to 1111, causing TCd to return HIGH. This transition of TCd can be used to clock a second 74193 counter for lower counts.