Understanding JK Flip-Flops: Race Condition & Master-Slave Design

Posted on Feb 18, 2025 in Computers

Understanding Race Conditions and Master-Slave JK Flip-Flops

The JK flip-flop diagram below represents the basic structure, which consists of Clock (CLK), Clear (CLR), and Preset (PR).

Race Around Condition in JK Flip-Flops

For a JK flip-flop, if J=K=1, and if clk=1 for a long period, the output Q will toggle as long as CLK remains high, making the output unstable or uncertain.

This is called a race around condition in a JK flip-flop.

We can overcome this problem by ensuring the clock =1 for a very short duration.

The circuit used to overcome race around conditions is called the Master-Slave JK flip-flop.

Master-Slave JK Flip-Flop

Here, two JK flip-flops are connected in series.

  • The first JK flip-flop is called the “master,” and the other is a “slave.”
  • The output from the master is connected to the two inputs of the slave, whose output is fed back to the inputs of the master.
  • The circuit also has an inverter in addition to the two flip-flops.
  • The Clock Pulse and inverter are connected, which causes the flip-flops to receive an inverted clock pulse.
  • In other words, if CP=0 for a master flip-flop, then CP=1 for a slave flip-flop, and vice versa.

Working of a Master-Slave Flip-Flop

  • When the clock pulse goes high, the slave is isolated; J and K inputs can affect the state of the system. The slave flip-flop is isolated when the CP goes low.
  • When the CP goes back to 0, information is transmitted from the master flip-flop to the slave flip-flop, and the output is obtained.
  • As the master flip-flop is positive triggered, it responds first, and the slave later (it is negative edge triggered).
  • The master goes to the K input of the slave when both inputs J=0 and K=1, and also Q’ = 1. In this case, the slave copies the master as the clock forces the slave to reset.
  • The master goes to the J input of the slave when both J=1 and K=0, Q = 1. The clock is set due to the negative transition of the clock.
  • There is a state of toggle when both J=1 and K=1. On the negative transition of the clock, the slave toggles, and the master toggles on the positive transition of the clock.
  • Both flip-flops are disabled when both J=0 and K=0, and Q is unchanged.

4-Bit Magnitude Comparator

A comparator used to compare two binary numbers, each of four bits, is called a 4-bit magnitude comparator. It consists of eight inputs (each for two four-bit numbers) and three outputs to generate less than, equal to, and greater than relationships between the two binary numbers.

In a 4-bit comparator, the condition of A>B can occur in the following four cases:

  1. If A3 = 1 and B3 = 0
  2. If A3 = B3 and A2 = 1 and B2 = 0
  3. If A3 = B3, A2 = B2 and A1 = 1 and B1 = 0
  4. If A3 = B3, A2 = B2, A1 = B1 and A0 = 1 and B0 = 0

Similarly, the condition for A

If A3 = 0 and B3 = 1 If A3 = B3 and A2 = 0 and B2 = 1 If A3 = B3, A2 = B2 and A1 = 0 and B1 = 1 If A3 = B3, A2 = B2, A1 = B1 and A0 = 0 and B0 = 1

The condition of A=B is possible only when all the individual bits of one number exactly coincide with the corresponding bits of another number.