USB 2.0 Communication with PIC18F4550 Microcontrollers

Posted on Dec 8, 2024 in Electronics

USB 2.0 Communication Features with PIC18F4550

Transfer Rate: It can be low speed (1.5 Mb/s) or high speed (12 Mb/s).

Start of Packet (SOP) and Interrupts: Every time there is a transmission or reception of data on the bus, it generates an interrupt to the PIC. The routine care must respond by managing all aspects of the low level of the USB specification. Thus, for the main application running on the microcontroller, USB protocol handling is transparent.

Endpoints: Allows the use of up to 32 Endpoints (16-way), but usually only 3 are used (Endpoint 0, 1, and 2). An endpoint is a buffer that stores data within the device (typically a record). In turn, each endpoint has a unique identifier that is assigned at the factory and a data flow direction (IN/OUT). All devices must support endpoint 0, which is used for configuration.

1-Kbyte Dual Access RAM: Banks 4 to 7 of the data memory are mapped to a special dual-port RAM. When the USB module is disabled, the GPRs in these banks are used like any other GPR data in memory. When the USB module is enabled, these memory banks are assigned as buffer RAM for USB operation. This area is shared between the microcontroller core and the Serial Interface Engine (SIE) and is used to transfer data directly between the two.

SIE (Serial Interface Engine): Responsible for generating the CRC, the synchronization of the signals D+ and D-, and proper communication between the module and the PIC. The UPS can be interfaced directly to the USB, using the internal transceiver, or it can be connected via a transceiver content.

Settings

USBEN: This is a priority bit at the beginning of the configuration, which enables or disables the USB module. It ignores all control and status bits when this is zero. This bit also activates the chip voltage regulator and connects the pull-up resistors, if allowed. Therefore, with USBEN, the software can connect or disconnect the USB. This bit can be found in the record UCON.

Setting the Frequency

For the implementation of USB communication, it is necessary to properly configure the PIC. A fundamental part of the configuration is the clock frequency. Depending on whether we work with the module in high speed or low speed (USB 2.0), we provide the module with 6 or 48 MHz, respectively. For this example, we will use the settings on USB 2.0 and a crystal connected to the PIC at 4 MHz.

Z

  • USBDIV = 1, so the timing passes through the PLL Prescaler.
  • PLL1 with what, to dispose of 4 MHz Fosc, the output is PLLDIV.
  • Keep those same 4 MHz.
  • CPUDIV1, maintaining the 4 MHz to time the system.

As you can see, we connect our crystal OSC1 and OSC2 at 4 MHz, but we could have used one of 8 MHz, 12 MHz, 16 MHz, 20 MHz, 24 MHz, 40 MHz, or 48 MHz, which are valid compatible options. Keep in mind that this crystal is the same one used to generate the required frequency of 48 MHz for USB 2.0 and the Clock of the PIC, which can be the same or not, depending on the configuration we eventually adopt. This means that we can have the USB at 48 MHz and our program in the PIC running at 12 MHz, for example.

After the Primary Trigger Oscillator, three parallel lines go to different modules with different possibilities.

  • The first line, the higher one, goes straight to the switch. If USBDIV is zero, it indicates that the original base frequency of the crystal is directly injected into the USB if the switch FSEN is also set to 1. This switch selects between the Primary Clock PLL or CPU. This option of directly injecting the crystal frequency is obviously only possible if we use a 48 MHz crystal, which is what we need for the USB. All other crystals must be treated to achieve the required 48 MHz.
  • The second line has to do with a PLL Prescaler (frequency divider). In each of its outlets, we are going to have FOSC divided by 1, 2, 3, 4, 5, 6, 10, or 12. And by PLLDIV (Multiplexer), we will select the one we want to use. So, if our crystal is 4 MHz and we put a 000 in PLLDIV, we are dividing by 1 the value of FOSC, resulting in 4 MHz at the output of the MUX. The output of MUX is what we use to inject the 96-MHz PLL. If we put 4 MHz into it, it generates 96 MHz. But 96 MHz is twice what we need for the USB, which is 48 MHz. Therefore, we immediately use a divider by 2, which is the second way in which we use USBDIV, and in this case, we will place a 1 for using the signal from the PLL.
  • The rest of the circuitry is associated with the configuration and allocation of the clock speed for the ALU.

Internal Transmitter

The USB peripheral has a low-speed transmitter internally connected to the SIE. This feature is useful in applications with a cheaper chip. The UTRDIS Bit (UCFG) controls the transmitter. They are allowed by default (UTRDIS = 0).

External Transmitter

This module provides support for the use of a transmitter outside the chip. The external transmitter is used in applications where physical conditions dictate the transmitter location away from the SIE. Transactions with an external transmitter are permitted when the UTRDIS bit = 1.

Internal Regulator

The PIC18FX455 device has a built-in 3.3 V regulator to provide power to the internal transmitter and provide a source for the pull-up internal and external 5V applications. For the regulator to be stable, it requires an external capacitor of 220nF (± 20%). The regulator is activated by default and can be disabled via the configuration bit (VREG = ON, OFF). When active, the voltage is visible on pin VUSB. When the regulator is disabled, you have to connect a 3.3 V to pin VUSB to power the internal transmitter.

USB specifications require 3.3 V in communications. However, the rest of the chip can operate at a higher voltage. Thus, the energy source of the transmitter is a separate source (VUSB).

BUS Speed

We can work with the module in high speed or low speed (USB 2.0). The UCFG register and Pull-Up resistors are responsible for this. The pull-up resistors, internal or external, are designed to meet the requirements of the USB “low speed” and “Full-Speed”. To operate in USB 2.0 mode, the FSEN bit in the UCFG register must be enabled. Once FSEN is enabled, the Pull-Up resistor is powered on pin D+ (This allows the peripheral device that connects to detect USB Full-Speed mode).

In low-speed mode, FSEN must be disabled, and the Pull-Up resistor that would be fed would be the D- (This will auto-detect low-speed mode).

Bit permission of Full-Speed (FSEN in UCFG):

  • 1 = Full-speed device and pull-up on D+ (Requires 48 MHz).
  • 0 = Low-speed device and pull-up in D- (Requires 6 MHz).

Activation Bit Pull-Up resistors (UPUEN in UCFG):

  • 1 = Pull-up enabled chip.
  • 0 = Pull-up the chip disabled.

USB speed, transmission, and pull-up need to be configured only during the activation of the module. Do not change these settings while the module is working.

USB Interrupts

The 18F4550 device has multiple interrupt sources and an interrupt priority that allows each interrupt source to be assigned a high priority level or a low priority. The highest priority pointer is the pointer to 000008h, and the low-priority interrupt is 000018h. Each interrupt source has three bits to control its operation. The functions of these bits are:

  • Flag to indicate that an interrupt has occurred.
  • The bit that lets you enable the interrupt.
  • The bit to select high priority or low priority.

Register PIR2

PIR2 contains the flag of the interruption of USB.

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

OSCIF CMIF USBIF EEIF BCLIF HLVIF TMR3IF CCP2IF

USBIF: Flag of USB:

  • 1 = The USB requests an interrupt (deleted by software).
  • 0 = The USB does not require interruption.

Register ft2

Ft2 permit contains the USB interrupt.

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

CMIE OSCI USBI BCLIE HLVIE TMR3IE CCP2IE

USBI: Permission Bit USB interrupt:

  • 1 = Interrupt enabled.
  • 0 = Interrupt disabled.

Register IPR2

IPR2 contains the priority bits of the interruption of USB.

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

CMIP OSCIP USBIP EEIP BCLIP HLVIP TMR3IP CCP2IP

USBIP: Bit of priority of the interruption of USB:

  • 1 = High priority.
  • 0 = Low priority.

Once the SAR activates a kill bit, you have to delete it by software, writing a ‘0’.

Control USB Endpoint

All USB devices are composed of a series of endpoints and a unique address assigned by the system. An endpoint is a buffer that stores data within the device. Each endpoint has a unique identifier that is assigned at the factory and a data flow direction (In, Out). All devices must support endpoint 0, which is used for configuration. Partnerships between the various endpoints of a device and the host are called Pipes. The Pipes allow you to move data between host software and device endpoint. Each Pipe is determined by the type of service, endpoint number, packet size, address, etc.

There are 4 different types of endpoints (Control, Bulk, Isochronous, and Interrupt), each used in a transfer type.

Each of the 16 possible bidirectional endpoints in the PIC18F4550 has a separate control register, UEPn (where ‘n’ represents the number of Endpoint). Each record has the same control bits.

Bit EPHSHK (UEPn) controls the exchange protocol endpoints. Enabling this bit enables the exchange protocol of USB. Typically, this bit is always set except when using synchronous endpoints. Bit EPCONDIS (UEPn) is used to enable or disable USB operations control (SETUP) with Endpoint. Deleting this bit allows transactions SETUP. Bits EPINE (UEPn) and EPOUTEN (UEPn) must be activated to allow input and output transactions. For Endpoint 0, this bit should always be deleted by the USB specifications identifying Endpoint 0 as the default control endpoint.