VHDL Code Examples: Unit Control HLSM and Button Press FSM
Unit Control HLSM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity UnitControl_HLSM is
port (clk, rst : in std_logic;
c : in std_logic;
A : in unsigned(7 downto 0);
z : out std_logic);
end UnitControl_HLSM;
architecture Behavior of UnitControl_HLSM is
begin
process(clk)
type UC_statetype is (UC_Init, UC_GetInput, UC_UnitOn);
variable UC_State : UC_statetype;
variable V : unsigned(7 downto 0);
begin
if (rising_edge(clk)) then
if (rst = '1') then
-- Initial state
UC_State := UC_Init;
else
-- State transitions
case UC_State is
when UC_Init =>
UC_State := UC_GetInput;
when UC_GetInput =>
if (V > 78) then
UC_State := UC_UnitOn;
elsif (not(V > 78)) then
UC_State := UC_GetInput;
end if;
when UC_UnitOn =>
if (c = '1') then
UC_State := UC_Init;
elsif ((not c) = '1') then
UC_State := UC_UnitOn;
end if;
when others =>
UC_State := UC_Init;
end case;
end if;
-- State actions
case UC_State is
when UC_Init =>
V := to_unsigned(0, 8);
z
when UC_GetInput =>
V := V + A;
when UC_UnitOn =>
z
when others =>
V := to_unsigned(0, 8);
z end case;
end if;
end process;
end Behavior;
Button Press FSM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ButtonPress_FSM is
port (clk, rst : in std_logic;
b : in std_logic;
y : out std_logic);
end ButtonPress_FSM;
architecture Behavior of ButtonPress_FSM is
begin
process(clk)
type BP_statetype is (BP_Init, BP_Out1, BP_Out2);
variable BP_State : BP_statetype;
begin
if (rising_edge(clk)) then
if (rst = '1') then
-- Initial state
BP_State := BP_Init;
else
-- State transitions
case BP_State is
when BP_Init =>
if ((not b) = '1') then
BP_State := BP_Init;
elsif (b = '1') then
BP_State := BP_Out1;
end if;
when BP_Out1 =>
BP_State := BP_Out2;
when BP_Out2 =>
BP_State := BP_Init;
when others =>
BP_State := BP_Init;
end case;
end if;
-- State actions
case BP_State is
when BP_Init =>
y
when BP_Out1 =>
y
when BP_Out2 =>
y
when others =>
y end case;
end if;
end process;
end Behavior;