VHDL Fundamentals: Entities, Architectures, and Syntax

Posted on Apr 6, 2025 in Computers

General Concepts

Design Tools:

  • CAD (Computer-Aided Design) <- Test
  • Simulation
  • EDA (Electronic Design Automation)

Basic VHDL Design Units

  • Entity: Defines the interface of a design block.
  • Architecture: Defines the behavior or structure of the design.
  • Package: Groups reusable declarations (types, components, functions, etc.).
  • Signal: Represents hardware wires or connections; used for communication between processes and components. Assignment operator: <=.
  • Variable: Used for temporary storage within sequential code (processes, functions, procedures). Assignment operator: :=.
  • Control Structures: Statements like IF/ELSE, CASE used within sequential code.

Entity

Defines the interface (input and output ports) of a design block without specifying its internal behavior or structure.

Entity Declaration Syntax

ENTITY entity_name IS
PORT (
    -- Port list: name : mode type;
    -- Example Modes: IN, OUT, INOUT, BUFFER
    port_name1 : IN std_logic;
    port_name2 : OUT std_logic_vector(7 DOWNTO 0);
    ...
);
END ENTITY entity_name; -- Optional: END entity_name;

Entity Examples

-- Example 1: Simple AND gate
ENTITY Example1 IS
PORT (
    a, b : IN  BIT;
    s    : OUT BIT
);
END ENTITY Example1;

-- Example 2: Multiplexer
ENTITY MUX1 IS
PORT (
    Data   : IN  BIT_VECTOR (3 DOWNTO 0);
    Select : IN  BIT_VECTOR (1 DOWNTO 0);
    Enable : IN  BIT;
    Sal    : OUT BIT -- 'Sal' likely means 'Output' in Spanish
);
END ENTITY MUX1;

Architecture

Describes how the design works internally, modeling the behavior or structure of the circuit defined by the entity. It can contain Register-Transfer Level (RTL) or behavioral descriptions. An entity can have multiple architectures associated with it.

Architecture Declaration Syntax

ARCHITECTURE architecture_name OF entity_name IS
    -- Declarations (signals, constants, components, types, etc.)
BEGIN
    -- Concurrent statements (logic implementation)
    -- Processes (sequential logic)
    -- Component instantiations
END ARCHITECTURE architecture_name; -- Optional: END architecture_name;

Architecture Example

-- Architecture for Example1 (AND gate)
ARCHITECTURE arch_example1 OF Example1 IS
BEGIN
    s <= a AND b; -- Concurrent signal assignment
END ARCHITECTURE arch_example1;

Port Modes

Define the direction of data flow for entity ports:

  • IN: Input port. Data flows into the entity.
  • OUT: Output port. Data flows out from the entity. Cannot be read internally in standard VHDL (pre-2008).
  • INOUT: Bidirectional port. Data can flow in both directions.
  • BUFFER: Output port whose value can also be read internally within the architecture. Often avoided; internal signals are generally preferred.

Common VHDL Data Types

  • INTEGER: Represents whole numbers. The range can be specified by the user or defaults to the compiler’s implementation range (typically 32-bit signed).
    • Example: VARIABLE count : INTEGER RANGE 0 TO 255;
    • Example: SIGNAL address : INTEGER RANGE 200 DOWNTO 54;
    • Default range example: SIGNAL index : INTEGER;
  • BIT: Represents a single binary digit (‘0’ or ‘1’). Part of the standard VHDL library.
  • BIT_VECTOR: An array (vector) of BIT values.
    • Example: SIGNAL data_bus : BIT_VECTOR (7 DOWNTO 0); — e.g., “01010101”
    • Example: SIGNAL flags : BIT_VECTOR (0 TO 3); — e.g., “1001”
  • STD_LOGIC: Standard logic type from the IEEE 1164 library. Represents multiple logic levels including ‘0’, ‘1’, ‘X’ (unknown), ‘Z’ (high impedance), ‘U’ (uninitialized), ‘W’ (weak unknown), ‘L’ (weak ‘0’), ‘H’ (weak ‘1’), ‘-‘ (don’t care). Strongly recommended over BIT.
  • STD_LOGIC_VECTOR: An array (vector) of STD_LOGIC values. Strongly recommended over BIT_VECTOR.
    • Example: SIGNAL control_word : STD_LOGIC_VECTOR (3 DOWNTO 0) := "0Z1X";
  • TIME: Represents simulation time units.
    • Example: CONSTANT delay_time : TIME := 20 ns;
    • Example: WAIT FOR 2.5 ps;

Bus Assignment Examples

Assigning values to vectors (buses), typically STD_LOGIC_VECTOR or BIT_VECTOR:

Full Bus Assignment

SIGNAL jose : STD_LOGIC_VECTOR(7 DOWNTO 0);
jose <= "11111111"; -- Assigns '1' to all 8 bits

Single Bit Assignment

SIGNAL dino : STD_LOGIC_VECTOR(7 DOWNTO 0);
dino(3) <= '1'; -- Assign '1' to the 4th bit (index 3)
dino(5) <= '0'; -- Assign '0' to the 6th bit (index 5)

Partial Bus (Slice) Assignment

SIGNAL pablo : BIT_VECTOR (7 DOWNTO 0); -- Signal Declaration
pablo(3 DOWNTO 2) <= "11"; -- Assign "11" to bits 3 and 2

Concatenation

Combining signals, slices, or literal values using the concatenation operator (&).

SIGNAL a : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL b : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL vilma : BIT_VECTOR (8 DOWNTO 0); -- Signal Declaration
-- Example assumes 'a' and 'b' are BIT_VECTOR or compatible
vilma <= a(1) & b(3 DOWNTO 0) & '0' & "010"; -- Concatenation example

Signal Assignment Types

Assignments made outside of a process block are concurrent.

Simple Concurrent Assignment

Directly assigns the result of an expression to a target signal. All concurrent assignments evaluate continuously.

signal_a <= input_r OR input_t;
signal_b <= (input_r OR input_t) AND NOT (input_g XOR input_h);
signal_c <= input_a AND input_b; -- Implements an AND gate
sum_result <= operand_y + operand_z; -- Implements an adder (requires numeric library)

Example within an architecture:

ENTITY Example2 IS
PORT (
    a, b : IN  BIT;
    c    : OUT BIT
);
END ENTITY Example2;

ARCHITECTURE arch_example2 OF Example2 IS
BEGIN
    c <= a AND b; -- Simple concurrent assignment
END ARCHITECTURE arch_example2;

Conditional Concurrent Assignment (WHEN/ELSE)

Assigns one of several expressions to a target signal based on the evaluation of boolean conditions. Conditions are evaluated sequentially (priority encoding).

-- General Form
target_signal <= expression1 WHEN condition1 ELSE
                 expression2 WHEN condition2 ELSE
                 ...
                 expressionN; -- Default assignment

-- Example: Flip-flop with asynchronous clear
q <= '0' WHEN clr = '1' ELSE -- Asynchronous clear has highest priority
     d WHEN rising_edge(clk) ELSE -- Synchronous data load
     q; -- No change otherwise (inferred memory, often needs a process)

-- Example: 2-to-1 Mux
-- Assumes an entity MUX2 with ports a, b, s (select), f (output)
ARCHITECTURE mux_arch OF MUX2 IS
BEGIN
    f <= a WHEN s = '0' ELSE b; -- Selects 'a' if s is '0', otherwise 'b'
END ARCHITECTURE mux_arch;

Selective Concurrent Assignment (WITH/SELECT/WHEN)

Assigns a value to a target signal based on the value of a selecting expression. All choices are evaluated in parallel (conceptually). Similar to a case statement for concurrent logic, often synthesizes to a multiplexer.

-- General Form
WITH selecting_expression SELECT
    target_signal <= expression1 WHEN choice1 | choice2, -- Multiple choices possible
                     expression2 WHEN choice3,
                     ...
                     expressionN WHEN OTHERS; -- Covers all other possible values

-- Example: 4-to-1 Mux
WITH sel SELECT -- sel is typically a 2-bit vector
    q <= data_a WHEN "00",
         data_b WHEN "01",
         data_c WHEN "10",
         data_d WHEN "11", -- Can use OTHERS instead of the last explicit choice
         default_value WHEN OTHERS; -- Important if sel can have other values ('X', 'Z' etc.)

Architecture Description Styles

Different ways to describe the hardware logic within an VHDL architecture:

Behavioral Style

Characterized by using sequential statements (like IF, CASE, LOOP) typical of programming languages, usually contained within a PROCESS block. It describes the algorithm or behavior step-by-step, without explicitly defining the gate-level structure. Suitable for complex control logic and state machines.

Note: Requires a PROCESS statement for sequential execution semantics.

Common target devices: CPLD (Complex Programmable Logic Device), FPGA (Field-Programmable Gate Array).

Dataflow Style

Models how data flows from inputs to outputs or between signals using concurrent signal assignments (<=), conditional assignments (WHEN/ELSE), and selective assignments (WITH/SELECT). It focuses on the data transformations and dependencies rather than sequential execution steps. PROCESS statements are generally not the primary construct for the main logic description in pure dataflow.

Structural Style

Describes the circuit as a hierarchical netlist, explicitly instantiating components (defined elsewhere, perhaps in libraries or other entity/architecture pairs) and connecting their ports using signals. It directly mirrors a schematic diagram composed of interconnected blocks.

Often requires declaring components using COMPONENT statements (which can be grouped in PACKAGEs) and mapping their ports using PORT MAP within the instantiation statement. Auxiliary signals are typically needed for internal connections.

Packages

Packages are used to group reusable declarations such as types, subtypes, constants, functions, procedures, and component declarations. They promote modularity and code reuse, allowing common elements to be defined once and used in multiple design files via the USE clause.

Package Declaration Syntax:

PACKAGE package_name IS
    -- Declarations (types, constants, functions, procedures, components)
END PACKAGE package_name;

-- Optional Package Body (required if functions/procedures are declared)
PACKAGE BODY package_name IS
    -- Function/Procedure implementations
END PACKAGE BODY package_name;

Mixed Style

Combines elements from behavioral, dataflow, and structural styles within a single architecture. This is a very common approach, allowing designers to use the most appropriate style for different parts of the design. For example, using a behavioral process for a sequential control unit and dataflow assignments or structural instantiations for the datapath logic.